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Intrinsically stretchable electronics with skin-like mechanical properties have been identified as a promising platform for emerging applications ranging from continuous physiological monitoring to real-time analysis of health conditions, to closed-loop delivery of autonomous medical treatment 1 – 7 . However, current technologies could only reach electrical performance at amorphous-silicon level (that is, charge-carrier mobility of about 1 cm 2  V −1  s −1 ), low integration scale (for example, 54 transistors per circuit) and limited functionalities 8 – 11 . Here we report high-density, intrinsically stretchable transistors and integrated circuits with high driving ability, high operation speed and large-scale integration. They were enabled by a combination of innovations in materials, fabrication process design, device engineering and circuit design. Our intrinsically stretchable transistors exhibit an average field-effect mobility of more than 20 cm 2  V −1  s −1 under 100% strain, a device density of 100,000 transistors per cm 2 , including interconnects and a high drive current of around 2 μA μm −1 at a supply voltage of 5 V. Notably, these achieved parameters are on par with state-of-the-art flexible transistors based on metal-oxide, carbon nanotube and polycrystalline silicon materials on plastic substrates 12 – 14 . Furthermore, we realize a large-scale integrated circuit with more than 1,000 transistors and a stage-switching frequency greater than 1 MHz, for the first time, to our knowledge, in intrinsically stretchable electronics. Moreover, we demonstrate a high-throughput braille recognition system that surpasses human skin sensing ability, enabled by an active-matrix tactile sensor array with a record-high density of 2,500 units per cm 2 , and a light-emitting diode display with a high refreshing speed of 60 Hz and excellent mechanical robustness. The above advancements in device performance have substantially enhanced the abilities of skin-like electronics. High-density, intrinsically stretchable transistors with high driving ability and integrated circuits with high operation speed and large-scale integration were enabled by a combination of innovations in materials, fabrication process design, device engineering and circuit design.

In this paper, we describe a channel self-alignment process to produce High-Voltage VDMOSFETs in 4H-SiC. We use polysilicon as a mask for two injection methods, Because the oxidation rate of polysilicon is different from that of silicon carbide, we can generate a certain thickness of silicon oxide flank wall by controlling the oxidation rate and time. Therefore, there will be a certain distance between the N+ source region and the Pbase region, and this distance is the length of the channel. Obviously, no pattern transfer occurs between the two ion implantation processes, so the channel is self-aligned. As long as the thickness of the side wall is controlled accurately, the channel length of sub-micron can be obtained.

Crystalline silicon (c-Si) photovoltaics has long been considered energy intensive and costly. Over the past decades, spectacular improvements along the manufacturing chain have made c-Si a low-cost source of electricity that can no longer be ignored. Over 125 GW of c-Si modules have been installed in 2020, 95% of the overall photovoltaic (PV) market, and over 700 GW has been cumulatively installed. There are some strong indications that c-Si photovoltaics could become the most important world electricity source by 2040–2050. In this Review, we survey the key changes related to materials and industrial processing of silicon PV components. At the wafer level, a strong reduction in polysilicon cost and the general implementation of diamond wire sawing has reduced the cost of monocrystalline wafers. In parallel, the concentration of impurities and electronic defects in the various types of wafers has been reduced, allowing for high efficiency in industrial devices. Improved cleanliness in production lines, increased tool automation and improved production technology and cell architectures all helped to increase the efficiency of mainstream modules. Efficiency gains at the cell level were accompanied by an increase in wafer size and by the introduction of advanced assembly techniques. These improvements have allowed a reduction of cell-to-module efficiency losses and will accelerate the yearly efficiency gain of mainstream modules. To conclude, we discuss what it will take for other PV technologies to compete with silicon on the mass market. Crystalline silicon solar cells are today’s main photovoltaic technology, enabling the production of electricity with minimal carbon emissions and at an unprecedented low cost. This Review discusses the recent evolution of this technology, the present status of research and industrial development, and the near-future perspectives.

Thin-film transistors (TFTs) are a key technology in large-area electronics and can be manufactured uniformly over large areas—on glass or flexible substrates—at lower processing temperatures and costs than complementary metal–oxide–semiconductor (CMOS)-based transistors. The transistors are used in established applications such as flat-panel displays and X-ray detectors, and are of potential use in a range of emerging applications. Here we discuss the development of TFTs for large-area electronics. We explore the use of TFTs—which can be based on hydrogenated amorphous silicon, low-temperature polycrystalline silicon, amorphous oxide semiconductors and organic semiconductors—in displays and sensors, as well as digital circuits and memory. We also consider their potential use in emerging applications such as neuromorphic computing. This Review examines the development of thin-film transistors for use in displays, sensors, digital circuits and memory, as well as their potential for future application in emerging technologies such as neuromorphic computing.

Thin-film transistors based on amorphous oxide semiconductors could be used to create low-cost backplane technology for large flat-panel displays. However, a trade-off between mobility and stability has limited the ability of such devices to replace current polycrystalline silicon technologies. Here we show that the sensitivity of amorphous oxide semiconductors to externally introduced impurities and defects is determined by the location of the conduction-band minimum and the relevant doping ability. Using bilayer-structured thin-film transistors, we identify the exact charge-trapping position under bias stress, which shows that the Fermi-level shift in the active layer can occur via electron donation from carbon-monoxide-related impurities. This mechanism is highly dependent on the location of the conduction-band minimum and explains why carbon-monoxide-related impurities greatly affect the stability of high-mobility indium tin zinc oxide transistors but not that of low-mobility indium gallium zinc oxide transistors. Based on these insights, we develop indium tin zinc oxide transistors with mobilities of 70 cm 2  (V s) –1 and low threshold voltage shifts of –0.02 V and 0.12 V under negative- and positive-bias temperature stress, respectively. By understanding the origins of instability in high-mobility amorphous oxide transistors, ultrastable thin-film transistors with mobilities of 70 cm 2  (V s) –1 can be fabricated.

The polysilicon reduction furnace is the key production equipment in the improved Siemens process. Variations in the internal flow velocity and temperature distribution significantly affect the reduction reaction and the deposition quality of polysilicon. In this work, the inlet velocity, silicon rod temperature, and inlet–outlet configuration of the furnace are selected as major influencing factors. A three-dimensional model of the furnace is built in NX, and simulations of the internal flow and temperature fields are conducted using Fluent. By comparing the optimal inlet velocity, silicon rod temperature, and structural configurations, this study provides guidance for improving the operational performance of industrial polysilicon furnaces.

This paper presents a material-aware comparative analysis of two-channel and three-channel nanosheet FinFETs (NS-FinFETs) designed at the 10 nm technology node using TCAD simulations. The study employs a gate-all-around (GAA) configuration combined with fully depleted silicon-on-insulator (FD-SOI) technology to enhance electrostatic integrity and short-channel control. Both devices are simulated under a fixed channel doping concentration of 1 × 10 18 cm −3 , and their performance is evaluated in terms of threshold voltage (V th ), subthreshold swing (SS), drain-induced barrier lowering (DIBL), on-current (I on ), off-current (I off ), I on /I off ratio, and transfer/output characteristics. The material stack considered in the design includes silicon (Si) as the channel material, silicon dioxide (SiO 2 ) as a conventional low-k dielectric, hafnium dioxide (HfO 2 ) as a high-k gate dielectric, n-type polysilicon (n-PolySi) as the gate electrode, and aluminum (Al) as the contact metal. Each material is selected for its compatibility with nanoscale CMOS fabrication and its role in balancing leakage suppression, electrostatic control, and drive current performance. The advantages of multi-channel architectures in achieving high-performance and energy-efficient designs. The findings highlight the importance of both channel engineering and material selection in optimizing nanosheet FinFETs for future low-power, high-performance technology nodes.

The photovoltaic industry is dominated by crystalline silicon solar cells. Although interdigitated back-contact cells have yielded the highest efficiency, both-sides-contacted cells are the preferred choice in industrial production due to their lower complexity. Here we show that omitting the layers at the front side that provide lateral charge carrier transport is the key to excellent optoelectrical properties for both-sides-contacted cells. This results in a conversion efficiency of 26.0%. In contrast to standard industrial cells with a front side p–n junction, this cell exhibits the p–n junction at the back surface in the form of a full-area polycrystalline silicon-based passivating contact. A detailed power-loss analysis reveals that this cell balances electron and hole transport losses as well as transport and recombination losses in general. A systematic simulation study led to some fundamental design rules for future >26% efficiency silicon solar cells and demonstrates the potential and the superiority of these back-junction solar cells. Front- and back-junction silicon photovoltaics dominate the market thanks to a lower manufacturing complexity compared with that of other device designs yet advances in efficiency remain elusive. Richter et al. now present an optimized design for the front and back junctions that leads to a 26.0%-efficient cell.

Polysilicon thin-film semiconductor bridges (SCB) and Pb•BaTNR primary explosives are selected to prepare SCB/Pb•BaTNR samples, and their ignition performance is tested. The test results show that the SCB/Pb•BaTNR samples were ignited random when the ignition energy provided for SCB is insufficient but aroud critical value. Under different energy-storage capacitance, the voltages that lead to SCB completely gasifying into high-energy plasma are around 21V, indicating that charging voltage is the main factor affecting SCB elements to produce high-energy plasma. Ignition tests are performed on the SCB/Pb•BaTNR samples under the conditions of 47μF/21V, 64μF/21V, and 100μF/21V. The samples are found to ignite reliably, and the action time ranges from 0.17 ms to 0.4 ms, meeting the requirements for high instantaneity.

Tunnel oxide passivated contact (TOPCon) silicon solar cells are rising as a competitive photovoltaic technology, seamlessly blending high efficiency with cost-effectiveness and mass production capabilities. However, the numerous defects from the fragile silicon oxide/c-Si interface and the low field-effect passivation due to the inadequate boron in-diffusion in p-type polycrystalline silicon (poly-Si) passivated contact reduce their open-circuit voltages ( V OC s), impeding their widespread application in the promising perovskite/silicon tandem solar cells (TSCs) that hold a potential to break 30% module efficiency. To address this, we have developed a highly passivated p-type TOPCon structure by optimizing the oxidation conditions, boron in-diffusion, and aluminium oxide hydrogenation, thus pronouncedly improving the implied V OC ( iV OC ) of symmetric samples with p-type TOPCon structures on both sides to 715 mV and the V OC of completed double-sided TOPCon bottom cells to 710 mV. Consequently, integrating with perovskite top cells, our proof of concept of 1 cm 2 n-i-p perovskite/silicon TSCs exhibit V OC s exceeding 1.9 V and a high efficiency of 28.20% (certified 27.3%), which paves a way for TOPCon cells in the commercialization of future tandems. Perovskite/silicon tandem solar cells have attracted great attention for their efficiency and industry-compatible fabrication. Here, authors report a p-type tunnel oxide passivated contact structure with improved implied open-circuit voltage, achieving efficiency over 28% in 1 cm 2 n-i-p tandem cells.