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Side-channel attacks are attacks against cryptographic devices that are based on information obtained by leakage into cryptographic algorithm hardware implementation rather than algorithm implementation. Power attacks are based on analyzing the power consumption of a corresponding input and obtaining access to this method. The power profile of the encryption circuit maintains an interaction with the input to be processed, allowing the attacker to guess the hidden secrets. In this work, we presented a novel architecture of masked logic cells that are resistant to power attacks and have reduced cell numbers. The presented masking cell reduces the relationship between the actual power and the mathematically approximated power model measured by the Pearson correlation coefficient. The security aspect of the logic cell is measured with the correlation coefficient of the person. The proposed mask-XOR and mask-AND cells are 0.0053 and 0.3respectively, much lower than the standard XOR and AND cells of 0.134 and 0.372respectively.

Embedded systems can be targeted by fault injection attacks (FIAs), which enable attackers to alter the system specified behavior, potentially gaining access to confidential information or causing unintended outcomes, among other effects. Although numerous security sensors and attack detectors have been proposed in the literature to detect different sources of FIAs, it is crucial to ensure that these mechanisms themselves have not been tampered. Hence, the integrity of these detectors is critical in maintaining the security of embedded systems. This study focuses on evaluating the robustness of delay-based digital detectors against a new type of FIA called power-off temperature attack (POTA). POTA occurs when the chip power is turned off, rendering the detectors inactive and allowing the attackers to bypass them. After a POTA, the circuit or its detectors may not function properly when the power is restored, potentially allowing other attacks to go undetected if the detectors are less sensitive. This study implements two attack detectors on Xilinx Artix-7 FPGAs and investigates the impact of heating cycles on theses detectors’ characteristics when the FPGA is in different states, including power-off, power-on, and inactive modes (such as clock-freezing mode). Our experiments reveal that heating cycles in power-off or inactive modes can alter the FPGA component delays and reduce the accuracy of its detectors, which highlights the vulnerability of these systems to POTA and potential risks to embedded system security.

The invention of smart low-power devices and ubiquitous Internet connectivity have facilitated the shift of many labour-intensive jobs into the digital domain. The shortage of skilled workforce and the growing food demand have led the agriculture sector to adapt to the digital transformation. Smart sensors and systems are used to monitor crops, plants, the environment, water, soil moisture, and diseases. The transformation to digital agriculture would improve the quality and quantity of food for the ever-increasing human population. This paper discusses the security threats and vulnerabilities to digital agriculture, which are overlooked in other published articles. It also provides a comprehensive review of the side-channel attacks (SCA) specific to digital agriculture, which have not been explored previously. The paper also discusses the open research challenges and future directions.

Power analysis attack is a form of side channel attack which can recover the key of a cryptographic algorithm running on some device. In this work we propose CAD based methodology to perform power analysis on pre-silicon gate-level netlist of cryptographic algorithm. We first build a new leakage model of the critical component present in crypto design by approximating it’s dynamic power consumption from the toggle count information. Then using the power model we perform power attack to recover key using power trace of crypto design. We validated our methodology on PRESENT like cipher structure and also compared our leakage model with popular Hamming distance and Hamming weight models, where we found our model requires very less number of power traces to recover keys with high correlation. We further extended our model to work by counting the number of toggles, that can be exploited by the circuit designers to early detect if their crypto design is vulnerable to any leakage or by tool developers to induct security awareness in their flow. Finally, we integrated our methodology with hybrid testing framework for first order side channel analysis to certify crypto-implementations from pre-silicon power analysis.

Currently, within the world, cybercrime is becoming increasingly rampant—often targeting civil infrastructure like power stations and other critical systems. A trend that is being noticed with these attacks is their increased use of embedded devices in denial-of-service (DoS) attacks. This creates a substantial risk to systems and infrastructures worldwide. Threats to embedded devices can be significant, and network stability and reliability can suffer, mainly through the risk of battery draining or complete system hang. This paper investigates such consequences through simulations of excessive loads, by staging attacks on embedded devices. Experimentation within Contiki OS focused on loads placed on physical and virtualised wireless sensor network (WSN) embedded devices by launching DoS attacks and by exploiting the Routing Protocol for Low Power and Lossy Networks (RPL). Results from these experiments were based on the metric of power draw, mainly the percentage increase over baseline and the pattern of it. The physical study relied on the output of the inline power analyser and the virtual study relied on the output of a Cooja plugin called PowerTracker. This involved experiments on both physical and virtual devices, and analysis of the power draws characteristics of WSN devices with a focus on embedded Linux platforms and Contiki OS. Experimental results provide evidence that peak power draining occurs with a malicious-node-to-sensor device ratio of 13-to-1. Results show a decline in power usage with a more expansive 16-sensor network after modelling and simulating a growing sensor network within the Cooja simulator.

The speech signals are affected by the background noise distortion that is unfavorable to both the intelligibility as well as the speech quality. Most of the speech processing algorithms function with the spectral magnitude without consideration of the spectral phase by leaving them unexplored and unstructured. The proposed single channel speech enhancement model called the Adaptive Recurrent Nonnegative Matrix Factorization (AR-NMF) is designed based on the phase compensation strategy with deep learning. The two major phases considered here are the training phase and the testing phase. During the process of training, the noisy speech signal is decomposed by the Hurst exponent-based Empirical Mode Decomposition (HEMD) and is converted into the frequency domain using Short Time Fourier Transform. Further, the new AR-NMF is used for denoising, where the tuning factor is optimally generated by the optimized RNN. Here, the hidden neurons are optimized using the proposed Adaptive Attack Power-based Sail Fish Optimization (AAP-SFO) with consideration of minimizing the Mean Absolute Error between the actual value and the predicted value. Finally, this phase compensated speech signal is given to the ISTFT that results in the final denoised clean speech signal. From the analysis, the CSED of AAP-SFO-AR-NMF for the street noise is 58.24%, 57.34%, 56.72%, and 77.37% more than RNMF, esHRNR, esTSNR, and Vuvuzela respectively. The performance of the proposed deep enhancement method is extensively evaluated and compared to diverse adverse noisy environments that describe the superiority of the proposed method.

SNOW3G 是由 ETSI/SAGE 于 2006 年基于 SNOW2.0 设计的流密码算法, 已被 3GPP 采纳为国际加密标准, 并在 4G/5G 移动通信中作为数据机密性算法和数据完整性算法的核心算法使用. 已有大量研究工作证明了 SNOW3G 算法足以抵御传统的密码分析攻击, 但很少有工作对该算法的具体实现进行分析, 验证算法抵抗侧信道攻击的能力. 本文以 3GPP 标准中 SNOW3G 的算法实现为研究对象, 从侧信道的角度出发在单片机上研究该算法的安全性, 提出了针对该算法的相关性能量攻击方法. 首先, 对 SNOW3G 的算法实现进行分析, 找到算法中存在能量泄漏的操作, 然后根据算法中密钥与该操作间的联系制定合理的攻击策略, 最终恢复出算法的密钥. 通过实验对提出的相关性能量攻击方法进行了验证, 结果表明, 在装有 ATMega128A 芯片的单片机上, 利用该方法仅需使用2000条能量消耗曲线即可在 1 小时内完整恢复出算法的密钥.

Increasing penetrations of interoperable distributed energy resources (DER) in the electric power system are expanding the power system attack surface. Maloperation or malicious control of DER equipment can now cause substantial disturbances to grid operations. Fortunately, many options exist to defend and limit adversary impact on these newly‐created DER communication networks, which typically traverse the public internet. However, implementing these security features will increase communication latency, thereby adversely impacting real‐time DER grid support service effectiveness. In this work, a collection of software tools called SCEPTRE was used to create a co‐simulation environment where SunSpec‐compliant photovoltaic inverters were deployed as virtual machines and interconnected to simulated communication network equipment. Network segmentation, encryption, and moving target defence security features were deployed on the control network to evaluate their influence on cybersecurity metrics and power system performance. The results indicated that adding these security features did not impact DER‐based grid control systems but improved the cybersecurity posture of the network when implemented appropriately.

There are several attacks that exploit the presence of side channels in hardware implementations of cryptographic algorithms to extract secret data. Differential power analysis (DPA) and simple power analysis (SPA) attacks sense the power consumption of the hardware to extract the secret cryptographic key. These attacks either directly examine the power traces or carry out statistical operations on the power traces obtained from the hardware while executing the cryptographic algorithm. This paper presents a circuit that can be added to crypto-hardware to suppress information leakage through the power supply pin side channel. We discuss the design, simulation results and the limitations of the suppression circuit. We show that this countermeasure significantly increases the number of power trace samples required to undertake a DPA attack. The countermeasure does not require any assumptions about the design of the hardware under protection.

侧信道攻击技术是国际密码学研究的热点方向, 它能够通过物理信道直接获得密码运算的中间信息, 也能够分段恢复较长的密钥, 因而它比传统密码分析更容易攻击实际密码系统. 目前国际主流的密码产品测评机构均把侧信道攻击的防护能力作为衡量设备或芯片安全性的主要指标, 但产品即使取得了权威的安全认证, 仍然可能会被侧信道攻击攻破. 本文归纳了近年来国际上的学者、黑客们利用侧信道攻击破解密码模块或安全产品的技术与案例, 分别从能量攻击、电磁辐射攻击、故障攻击、中距离电磁与声音攻击、缓存攻击等角度进行详细阐述, 并对未来发展趋势进行了探讨. 尤其是近三年内, 物联网设备、工业控制系统、手机、智能终端等流行设备都成了侧信道攻击者们热衷研究的对象, 多种常见密码设备已被侧信道攻击技术破解, 为个人财产、集体利益带来了极大的安全威胁. 希望能够通过本文的综述, 引起业界对物理安全问题的高度重视, 新产品在快速研发、占领市场的同时, 也应达到足够的安全等级.