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Intelligent computing paradigms have become increasingly important for the efficient processing of massive amounts of data. However, using traditional electronic devices to implement these intelligent paradigms is currently mismatched and limited by their energy, area, and speed. Spintronics, which exploits the magnetic and electrical properties of electrons, could break through these limitations and bring new possibilities to electrical devices. In particular, the tunneling magnetoresistance effect, merging quantum and spintronics, enables spintronic devices to be compatible with standard integrated circuits with a magnetic tunnel junction (MTJ) design, showing great potential for implementing hardware-based intelligent frameworks. In this review, we introduce the specific capabilities of MTJs, including nonvolatility, stochasticity, plasticity, and nonlinearity, which are highly favorable in artificial intelligence algorithms. We then present how these devices could impact the development of intelligent computing, including in-memory computing, probabilistic computing, and neuromorphic computing. Finally, we discuss their challenges and perspectives in intelligent hardware implementations.

Probabilistic computing, a class of physics-based computing, bridges the gap between quantum computing and the classical von Neumann architecture. This approach provides more efficient means of addressing NP problems, which are challenging for classical computers. In this work, we analyze the core concept of probabilistic computing which is based on the Ising model framework—including bit fluctuations and energy trends. In addition, we extend the traditional binary (two-level) system into a multi-level probabilistic framework, i.e. number partitioning problem to multiway number partitioning problem, as a case study.

In this work, an innovative design model aimed at enhancing the efficacy of ground-state probabilistic logic with a binary energy landscape (GSPL-BEL) is presented. This model enables the direct conversion of conventional CMOS-based logic circuits into corresponding probabilistic graphical representations based on a given truth table. Compared to the conventional approach of solving the configuration of Ising model-basic probabilistic gates through linear programming, our model directly provides configuration parameters with embedded many-body interactions. For larger-scale probabilistic logic circuits, the GSPL-BEL model can fully utilize the dimensions of many-body interactions, achieving minimal node overhead while ensuring the simplest binary energy landscape and circumventing additional logic synthesis steps. To validate its effectiveness, hardware implementations of probabilistic logic gates were conducted. Probabilistic bits were introduced as Ising cells, and cascaded conventional XNOR gates along with passive resistor networks were precisely designed to realize many-body interactions. HSPICE circuit simulation results demonstrate that the probabilistic logic circuits designed based on this model can successfully operate in free, forward, and reverse modes, exhibiting the simplest binary probability distributions. For a 2-bit × 2-bit integer factorizer involving many-body interactions, compared to the logic synthesis approach, the GSPL-BEL model significantly reduces the number of consumed nodes, the solution space (in the free-run mode), and the number of energy levels from 12, 4096, and 9–8, 256, and 2, respectively. Our findings demonstrate the significant potential of the GSPL-BEL model in optimizing the structure and performance of probabilistic logic circuits, offering a new robust tool for the design and implementation of future probabilistic computing systems.

As social networks and related data processes have grown exponentially in complexity, the efficient resolution of combinatorial optimization problems has become increasingly crucial. Recent advancements in probabilistic computing approaches have demonstrated significant potential for addressing these problems more efficiently than conventional deterministic computing methods. In this study, we demonstrate a highly durable probabilistic bit (p‐bit) device utilizing two‐dimensional materials, specifically hexagonal boron nitride (h‐BN) and tin disulfide (SnS2) nanosheets. By leveraging the inherently stochastic nature of electron trapping and detrapping at the h‐BN/SnS2 interface, the device achieves durable probabilistic fluctuations over 108 cycles with minimal energy consumption. To mitigate the static power consumption, we integrated an active switch in series with a p‐bit device, replacing conventional resistors. Furthermore, employing the pulse width as the control variable for probabilistic switching significantly enhances noise immunity. We demonstrate the practical application of the proposed p‐bit device in implementing invertible Boolean logic gates and subsequent integer factorization, highlighting its potential for solving complex combinatorial optimization problems and extending its applicability to real‐world scenarios such as cryptographic systems. This study introduces a novel probabilistic bit (p‐bit) device utilizing advanced materials, hexagonal boron nitride (h‐BN) and tin disulfide (SnS2), to enhance durability and energy efficiency in computational applications. By leveraging the stochastic behavior of electron trapping and detrapping at the h‐BN/SnS2 interface, the device achieves reliable performance over 108 cycles with minimal energy consumption. This innovation has significant implications for solving complex optimization problems and developing energy‐efficient alternatives to quantum computing for tasks such as cryptography and integer factorization.

Photonic neural networks (PNNs) based on silicon photonic integrated circuits (Si‐PICs) offer significant advantages over microelectronic counterparts, including lower energy consumption, higher bandwidth, and faster computing speeds. However, the analog nature of optical signal in PNNs makes Si‐PIC solutions highly sensitive to device noise, especially when using fixed‐value deterministic models, which are not robust to hardware fluctuation. Furthermore, current PNNs are unable to handle data uncertainty, a critical factor in applications such as autonomous driving, medical diagnostics, and financial forecasting. Herein, a photonic Bayesian neural network (PBNN) architecture that incorporates Bayesian principles to enhance robustness and address uncertainty is proposed. In the PBNN, device noise is leveraged through photonic‐noise‐based random number generators, which combine Mach‐Zehnder interferometers and micro‐ring resonators to independently control output mean and standard deviation. Based on modelling with experimentally extracted data, the PBNN achieves a classification accuracy of up to 98% for handwritten digit recognition, matching full‐precision models on conventional computers. Beyond classification, the PBNN excels in multimodal data processing, regression, and outlier detection. This scalable, energy‐efficient architecture transforms photonic noise into computational value, addressing the limitations of deterministic PNNs and enabling uncertainty‐aware computing for real‐world applications. This work introduces a novel photonic Bayesian neural network architecture that utilizes tunable photonic random number generators to independently control weight distribution parameters, significantly improving robustness, scalability, and accuracy while demonstrating practical applications in multimodal data processing and uncertainty‐aware computing.

Modern machine learning is based on powerful algorithms running on digital computing platforms and there is great interest in accelerating the learning process and making it more energy efficient. In this paper we present a fully autonomous probabilistic circuit for fast and efficient learning that makes no use of digital computing. Specifically we use SPICE simulations to demonstrate a clockless autonomous circuit where the required synaptic weights are read out in the form of analog voltages. This allows us to demonstrate a circuit that can be built with existing technology to emulate the Boltzmann machine learning algorithm based on gradient optimization of the maximum likelihood function. Such autonomous circuits could be particularly of interest as standalone learning devices in the context of mobile and edge computing.

This paper delves into the subject of outlier detection techniques tailored for unique datasets related to residential energy consumption. Building upon the current state of research [1] we introduce the Grubbs and Z-score methods and investigate a range of outlier detection strategies encompassing statistical, probabilistic, and machine learning algorithms. The findings underscore the importance of outlier detection in the Romanian residential energy sector.

As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future is retaining high reliability in the presence of faulty devices and noise. Probabilistic computing offers one possible approach. In this paper we describe our approach for mapping circuits onto CMOS using principles of probabilistic computation. In particular, we demonstrate how Markov random field elements may be built in CMOS and used to design combinational circuits running at ultra low supply voltages. We show that with our new design strategy, circuits can operate in highly noisy conditions and provide superior noise immunity, at reduced power dissipation. If extended to more complex circuits, our approach could lead to a paradigm shift in computing architecture without abandoning the dominant silicon CMOS technology.[PUBLICATION ABSTRACT]

We propose a new matching algorithm -- Unpaired kidney exchange -- to tackle the problem of double coincidence of wants without using money. The fundamental idea is that \"memory\" can serve as a medium of exchange. In a dynamic matching model with heterogeneous agents, we prove that average waiting time under the Unpaired algorithm is close to optimal, substantially less than the standard pairwise and chain exchange algorithms. We evaluate this algorithm using a rich dataset of kidney patients in France. Counterfactual simulations show that the Unpaired algorithm can match 57% of the patients, with an average waiting time of 440 days (state-of-the-art algorithms match about 34% with an average waiting time of 695 days). The optimal algorithm, which is practically infeasible, performs only slightly better: it matches 58% of the patients and leads to an average waiting time of 426 days. The Unpaired algorithm confronts two incentive-related practical challenges. We address those challenges via a modified version of the Unpaired algorithm that employs kidneys from the deceased donors waiting list. It can match 86% of the patients, while reducing the average waiting time to about 155 days.

This chapter contains sections titled: What is Computational Intelligence? Classical Components of CI Hybrid Intelligent Systems in CI Emerging Trends in CI Summary References