Explore the vast range of titles available.

In order to improve the efficiency of on-chip debugging, a fast on-chip debugging design is proposed, which adopts JTAG interface and is applied in RISC-V processor. In this paper, we extend some debugging instructions, effectively reducing data entry by operating the debugging bus directly, and realize the breakpoint, pause, single step, et al., providing conveniences for the development and debugging of the software system.

Information security is a fundamental and urgent issue in the digital transformation era. Cryptographic techniques and digital signatures have been applied to protect and authenticate relevant information. However, with the advent of quantum computers and quantum algorithms, classical cryptographic techniques have been in danger of collapsing because quantum computers can solve complex problems in polynomial time. Stemming from that risk, researchers worldwide have stepped up research on post-quantum algorithms to resist attack by quantum computers. In this review paper, we survey studies in recent years on post-quantum cryptography (PQC) and provide statistics on the number and content of publications, including a literature overview, detailed explanations of the most common methods so far, current implementation status, implementation comparisons, and discussion on future work. These studies focused on essential public cryptography techniques and digital signature schemes, and the US National Institute of Standards and Technology (NIST) launched a competition to select the best candidate for the expected standard. Recent studies have practically implemented the public key encryption/key encapsulation mechanism (PKE/KEM) and digital signature schemes on different hardware platforms and applied various optimization measures based on other criteria. Along with the increasing number of scientific publications, the recent trend of PQC research is increasingly evident and is the general trend in the cryptography industry. The movement opens up a promising avenue for researchers in public key cryptography and digital signatures, especially on algorithms selected by NIST.

At INFN-T1 we recently acquired some nodes with ARM and RISC-V CPUs to understand the experiment level of readiness on new hardware solutions and to test our production pipelines. After some initial testing, ARM resources entered the standard farm, since the stability both of the nodes and of the software was production quality ready. On the contrary RISC-V solutions are still to be considered only as testbed, since the software is not ready for general production. In this article we will describe all the activities that were necessary to enable users to run on ARM and RISC-V and will give some figures on performance, compared to x86_64 counterpart. In the end we will try to describe our point of view for the possible mass adoption of this architecture in Tier1 data centers.

In pursuit of energy-efficient solutions for computing in High Energy Physics (HEP) we have extended our investigations of non-x86 architectures beyond the ARM platforms that we have previously studied. In this work, we have taken a first look at the RISC-V architecture for HEP workloads, leveraging advancements in both hardware and software maturity. We introduce the Pioneer Milk-V, a 64-core RISC-V machine running Fedora Linux, as our new testbed, available at ScotGrid Glasgow (UK) and INFN Bologna and Pisa (Italy). Despite this early stage of RISC-V adoption in HEP, significant progress has been made in software compatibility. Standard frameworks such as ROOT, Geant4, CVMFS, and XRootD can be successfully built and run on the RISC-V platform, showcasing the evolving ecosystem. Additionally, efforts are underway to port CMSSW, promising further integration of HEP experiment software. In this first study, we assess performance and power efficiency, and we leverage various benchmarking tools to compare the RISC-V system with existing ARM and x86 architectures. Although it is not yet possible to run the HEPScore suite, we have conducted other tests such as running ROOT, DB12 and Geant4 benchmarks, while assessing and comparing performance per Watt across various platforms. These early results suggest that RISC-V architecture, despite being still immature for large scale adoption, holds potential for entering the increasingly heterogeneous computing landscape of HEP.

Neural network accelerator performs well in the research and verification of neural network models. In this paper, a convolutional neural network accelerator system composed of RISC-V processor core and Gemmini array accelerator is designed in Chisel language within the Chipyard framework, and the acceleration effect of different Gemmini array configurations for different input matrices is further investigated. The result shows that the accelerator system can achieve thousands of times acceleration compared with a single processor for large matrix calculations.

PRICING INSURANCE RISK A comprehensive framework for measuring, valuing, and managing risk Pricing Insurance Risk: Theory and Practice delivers an accessible and authoritative account of how to determine the premium for a portfolio of non-hedgeable insurance risks and how to allocate it fairly to each portfolio component. The authors synthesize hundreds of academic research papers, bringing to light little-appreciated answers to fundamental questions about the relationships between insurance risk, capital, and premium. They lean on their industry experience throughout to connect the theory to real-world practice, such as assessing the performance of business units, evaluating risk transfer options, and optimizing portfolio mix. Readers will discover: * Definitions, classifications, and specifications of risk * An in-depth treatment of classical risk measures and premium calculation principles * Properties of risk measures and their visualization * A logical framework for spectral and coherent risk measures * How risk measures for capital and pricing are distinct but interact * Why the cost of capital, not capital itself, should be allocated * The natural allocation method and how it unifies marginal and risk-adjusted probability approaches * Applications to reserve risk, reinsurance, asset risk, franchise value, and portfolio optimization Perfect for actuaries working in the non-life or general insurance and reinsurance sectors, Pricing Insurance Risk: Theory and Practice is also an indispensable resource for banking and finance professionals, as well as risk management professionals seeking insight into measuring the value of their efforts to mitigate, transfer, or bear nonsystematic risk.

Learn computer architecture with Python and ARM, simulating assembly program execution and designing a computer simulator Purchase of the print or Kindle book includes a free PDF eBook Key Features Build a computer simulator with Python: Learn computer architecture by designing and constructing a simulatorPython for architecture: Use Python to simulate and execute assembly language instructionsARM programming on Raspberry Pi: Explore ARM assembly language and run programs on Raspberry Pi Book Description This comprehensive guide offers a unique and immersive learning experience by combining Python programming with ARM architecture. Starting with an introduction to computer architecture and the flow of data within a computer system, you’ll progress to building your own interpreter using Python. You’ll see how this foundation enables the simulation of computer operations and learn ways to enhance a simulator by adding new instructions and displaying improved results. As you advance, you’ll explore the TC1 Assembler and Simulator Program to gain insights into instruction analysis and explore practical examples of simulators. This will help you build essential skills in understanding complex computer instructions, strengthening your grasp of computer architecture. Moreover, you’ll be introduced to the Raspberry Pi operating system, preparing you to delve into the detailed language of the ARM computer. This includes exploring the ARM instruction set architecture, data-processing instructions, subroutines, and the stack. With clear explanations, practical examples, and coding exercises, this resource will enable you to design and construct your own computer simulator, simulate assembly language programs, and leverage the Raspberry Pi for ARM programming. What you will learn Master the core principles of computer architectureUnderstand the role of registers, memory, and data flow in computersDiscover how to design and implement a computer simulator using PythonSimulate and execute assembly language programs on the simulatorEnhance the simulator using new instructions for improved outputAnalyze complex computer instructions for deeper architectural understandingExplore the ARM instruction set and data processing on the Raspberry PiDevelop proficiency in writing, assembling, and running ARM code on the Raspberry Pi Who this book is for This book is for university students studying computer science, particularly those enrolled in a computer architecture module. With its practical approach and succinct explanations, it is also suitable for hobbyists, enthusiasts, and self-learners seeking a deeper understanding of computer systems. The book assumes foundational knowledge of number bases, binary arithmetic, and Boolean logic concepts. While it primarily caters to the computer science field, this book is less geared toward electrical or electronics engineering.

In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource-constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 μJ.

Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal–oxide–semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems. A 16-bit microprocessor built from over 14,000 carbon nanotube transistors may enable energy efficiency advances in electronics technologies beyond silicon.

Nearly 50 years ago, Intel created the world’s first commercially produced microprocessor—the 4004 (ref. 1 ), a modest 4-bit CPU (central processing unit) with 2,300 transistors fabricated using 10 μm process technology in silicon and capable only of simple arithmetic calculations. Since this ground-breaking achievement, there has been continuous technological development with increasing sophistication to the stage where state-of-the-art silicon 64-bit microprocessors now have 30 billion transistors (for example, the AWS Graviton2 (ref. 2 ) microprocessor, fabricated using 7 nm process technology). The microprocessor is now so embedded within our culture that it has become a meta-invention—that is, it is a tool that allows other inventions to be realized, most recently enabling the big data analysis needed for a COVID-19 vaccine to be developed in record time. Here we report a 32-bit Arm (a reduced instruction set computing (RISC) architecture) microprocessor developed with metal-oxide thin-film transistor technology on a flexible substrate (which we call the PlasticARM). Separate from the mainstream semiconductor industry, flexible electronics operate within a domain that seamlessly integrates with everyday objects through a combination of ultrathin form factor, conformability, extreme low cost and potential for mass-scale production. PlasticARM pioneers the embedding of billions of low-cost, ultrathin microprocessors into everyday objects. Flexible electronic platforms would enable the integration of functional electronic circuitry with many everyday objects; here, a low-cost and fully flexible 32-bit microprocessor is produced.