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Lightweight Cryptography (LWC) is widely used to provide integrity, secrecy and authentication for the sensitive applications. However, the LWC is vulnerable to various constraints such as high-power consumption, time consumption, and hardware utilization and susceptible to the malicious attackers. In order to overcome this, a lightweight block cipher namely PRESENT architecture is proposed to provide the security against malicious attacks. The True Random Number Generator-Pseudo Random Number Generator (TRNG-PRNG) based key generation is proposed to generate the unpredictable keys, being highly difficult to predict by the hackers. Moreover, the hardware utilization of PRESENT architecture is optimized using the Dual port Read Only Memory (DROM). The proposed PRESENT-TRNG-PRNG architecture supports the 64-bit input with 80-bit of key value. The performance of the PRESENT-TRNG-PRNG architecture is evaluated by means of number of slice registers, flip flops, number of slices Look Up Table (LUT), number of logical elements, slices, bonded input/output block (IOB), frequency, power and delay. The input retrieval performances analyzed in this PRESENT-TRNG-PRNG architecture are Peak Signal to Noise Ratio (PSNR), Structural Similarity Index (SSIM) and Mean-Square Error (MSE). The PRESENT-TRNG-PRNG architecture is compared with three different existing PRESENT architectures such as PRESENT On-The-Fly (PERSENT-OTF), PRESENT Self-Test Structure (PRESENT-STS) and PRESENT-Round Keys (PRESENT-RK). The operating frequency of the PRESENT-TRNG-PRNG is 612.208 MHz for Virtex 5, which is high as compared to the PRESENT-RK.

In this paper, all-optical 2-to-4 line decoder and read-only memory (ROM) are analyzed using a Reflective Semiconductor Optical Amplifier (RSOA) based optical switch. The structures of these 2-to-4 line decoder and read only memory are very simple and the operating speed is 200 Gbps, which can be used in optical hardware systems. The 2-to-4 line decoder output shows a very high extension ratio (ER), contrast ratio (CR), and value. These high values indicate the distinguishment between two states (‘1’ and ‘0’) very clearly.

In recent times, any device should be designed with taken care of power consumption as well as speed. Photon has super-fast speed so it is very preferable to the researcher rather than the electron. So the researchers focus on the development of low-power-consuming devices. The reflective semiconductor optical amplifier (RSOA) is a suitable candidate for that purpose. It has a versatile gain medium and also it has huge application in passive optical networks. In this article, we have proposed a design of read-only memory using RSOA. To verify the practical feasibility, we have used MATLAB software to simulate the design. For all the memory outputs, the quality factor ( Q ), extinction ratio, contrast ratio, and also bit error rate have been calculated.

A switching memory device based on functionalized gold nanoparticles (AuNPs) and hexagonal copper sulfide nanocrystals (CuS), finely blended in polymethylmethacrylate matrix (PMMA), is herein presented. A two-electrode sandwich architecture has been implemented using aluminum top and bottom electrodes and a polymeric insulating layer based on PMMA/AuNPs/CuS. The device showed memory storage capabilities suitable for (Read Only Memory) ROM applications and behaves as a typical Write-Once, Read-Many-times (WORM) device. The results obtained with the blend containing AuNPs and/or CuS were compared with pure PMMA. By a voltage ramp in the range ± 9 V, it was possible to permanently change the electrical resistance between the electrodes yielding an ON/OFF current ratio above 10 5 with long-term stability over the whole experiment duration (30 days).

We construct quantum circuits that exactly encode the spectra of correlated electron models up to errors from rotation synthesis. By invoking these circuits as oracles within the recently introduced “qubitization” framework, one can use quantum phase estimation to sample states in the Hamiltonian eigenbasis with optimal query complexityO(λ/ε), whereλis an absolute sum of Hamiltonian coefficients andεis the target precision. For both the Hubbard model and electronic structure Hamiltonian in a second quantized basis diagonalizing the Coulomb operator, our circuits have T-gate complexityO(N+log(1/ε)), whereNis the number of orbitals in the basis. This scenario enables sampling in the eigenbasis of electronic structure Hamiltonians with T complexityO(N3/ε+N2log(1/ε)/ε). Compared to prior approaches, our algorithms are asymptotically more efficient in gate complexity and require fewer T gates near the classically intractable regime. Compiling to surface code fault-tolerant gates and assuming per-gate error rates of one part in a thousand reveals that one can error correct phase estimation on interesting instances of these problems beyond the current capabilities of classical methods using only about a million superconducting qubits in a matter of hours.

This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

Anisotropy is a manifestation of lowered symmetry in material systems that have profound fundamental and technological implications. For van der Waals magnets, the two-dimensional (2D) nature greatly enhances the effect of in-plane anisotropy. However, electrical manipulation of such anisotropy as well as demonstration of possible applications remains elusive. In particular, in-situ electrical modulation of anisotropy in spin transport, vital for spintronics applications, has yet to be achieved. Here, we realized giant electrically tunable anisotropy in the transport of second harmonic thermal magnons (SHM) in van der Waals anti-ferromagnetic insulator CrPS 4 with the application of modest gate current. Theoretical modeling found that 2D anisotropic spin Seebeck effect is the key to the electrical tunability. Making use of such large and tunable anisotropy, we demonstrated multi-bit read-only memories (ROMs) where information is inscribed by the anisotropy of magnon transport in CrPS 4 . Our result unveils the potential of anisotropic van der Waals magnons for information storage and processing. The anisotropic electrical and optical response of materials has allowed for the development of variety of sensors, memories and other interesting devices. Here, Qi et al turn their attention to the van der Waals antiferromagnetic insulator CrPS 4 , and demonstrate a very large, electrically tunable anisotropy in magnon transport, and present a multibit read-only memory based on this anisotropy.

Memory performance has become the major bottleneck to improve the overall performance of the computer system. By using memory controller, there is effective control of data between processor and memory. In this paper, a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint random verification environment is built for the designed memory controller. Verification plays an important role in any design flow as it is done before silicon development. It is done at time of product development for quality checking and bug fixing in design.

Gold film electrodes (Au-FE) with distinct nanostructured patterns were prepared from polycarbonate (PC) substrates and investigated with respect to their analytical sensitivity. The recordable (R) and read-only memory (ROM) discs, respectively, yield PC substrates with grooves (stripe pattern) or pits (indented pattern). The Au-FEs were characterized in terms of surface morphology and surface patterns, and it was found that the surface area of all Au-FEs does not significantly differ (by 0.2 to 7.4 %) compared to electrode with flat surfaces. However, the electrical signal of indented patterns is larger by 32 to 213 % when directly compared to stripe-patterned Au-FEs (at the same scale of groove and pit). An Au-FE prepared from a polycarbonate sheet from a Blu-ray disc read only memory (BD-ROM) as substrate displayed the best electrochemical performance towards reductive sensing of H 2 O 2 . The respective calibration plot, acquired at a working potential of −0.1 V vs. Ag/AgCl, covers the 0 to 10 mM hydrogen peroxide concentration range. The sensitivity is as high as 3.11 μA∙mM −1 ∙cm −2 which is larger by a factor of 28 compared to flat gold electrodes, and the detection limit (at a signal-to-noise ratio of 3) is 6 μM. Therefore, the results confirm that the indented nanopattern on the Au-FE significantly increases the efficiency of electrochemical detection. Conceivably, the surface patterns and structures may be designed in order to tune sensitivity with respect to future applications of Au-FEs in diagnostics, agriculture, and environmental monitoring. Graphical abstract Surface pattern of gold film electrode is a significant characteristic that improves sensitivity in electrochemical detection of hydrogen peroxide. Simple fabrication process is achieved using optical discs with two distinct patterns. The indented pattern from a Blu-ray disc read only memory (BD-ROM) offers over 28-fold sensitivity enhancement compared to flat surface.

We propose an improved RLizard implementation method that enables the RLizard key encapsulation mechanism (KEM) to run in a resource-constrained Internet of Things (IoT) environment with an 8-bit micro controller unit (MCU) and 8–16 KB of SRAM. Existing research has shown that the proposed method can function in a relatively high-end IoT environment, but there is a limitation when applying the existing implementation to our environment because of the insufficient SRAM space. We improve the implementation of the RLizard KEM by utilizing electrically erasable, programmable, read-only memory (EEPROM) and flash memory, which is possessed by all 8-bit ATmega MCUs. In addition, in order to prevent a decrease in execution time related to their use, we improve the multiplication process between polynomials utilizing the special property of the second multiplicand in each algorithm of the RLizard KEM. Thus, we reduce the required MCU clock cycle consumption. The results show that, compared to the existing code submitted to the National Institute of Standard and Technology (NIST) PQC standardization competition, the required MCU clock cycle is reduced by an average of 52%, and the memory used is reduced by approximately 77%. In this way, we verified that the RLizard KEM works well in our low-end IoT environments.