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Security threats in the integrated circuit (IC) supply chain are intensifying as demand drives fabrication to off-shore, potentially untrusted foundries. To mitigate theft and reverse engineering, recent work has focused on logic locking, encryption, and camouflaging. This paper introduces a probabilistic logic-driven algorithm that selects optimal locations for polymorphic gate replacement to strengthen circuit protection. Our approach leverages emerging polymorphic devices—namely the Giant Spin-Hall Effect (GSHE) switch, the 5-terminal magnetic domain wall motion (DWM) device, and the threshold-voltage-defined (TVD) switch—to diversify functional behavior and obscure true circuit intent. Evaluated on ISCAS-85 and ISCAS-89 benchmarks under state-of-the-art SAT and AppSAT Attacks, the proposed method substantially increases decryption time while achieving a marked improvement in Output Corruption Rate (OCR) relative to prior techniques. In particular, by deploying the GSHE Switch at the highest-probability nodes, we achieve more than 40% OCR along with strong resilience against SAT and AppSAT Attacks, further demonstrating the effectiveness of the proposed approach as a practical and scalable hardware obfuscation strategy.

The current trend of globalization of the supply chain in the integrated circuit (IC) industry has led to numerous security issues, such as intellectual property (IP) piracy, overbuilding, hardware Trojan (HT), and so on. Over the past decade or so, logic locking has been developed as an important method to prevent or mitigate the above security issues in ICs throughout their lifecycles. However, most published logic locking schemes are vulnerable to the SAT attack and its variants. Existing SAT-resilient locking schemes always entail a trade-off between security and effectiveness and incur significant hardware overhead. In this paper, we propose a new replacement-based key-controlled circuit (called RKC), the application of which changes the underlying framework of traditional logic locking designs, making the SAT attack and its variants infeasible in the framework. To achieve stronger functional and structural obfuscation and to validate the extensibility of the proposed method within the modified logic-locking design framework, we develop a new multi-input key-controlled circuit (called MKC) via vertical extension, also based on replacement applied to the locking design. In addition, we expand the two proposed circuits horizontally by varying the design parameter m, yielding four logic-locking design circuits. Relevant experiments performed on six selected benchmark circuits from ISCAS’85 and MCNC benchmarks show that the proposed method demonstrates superior/less hardware overhead compared to four recently published locking methods, i.e., GateLock, SKG-Lock, SKG-Lock+, and CAS-Lock.

An increasingly popular method for defending an integrated circuit (IC) against theft, excess production, and the Hardware Trojans (HT) is logic locking. The majority of popular logical locking approaches were also susceptible to the SAT attacks. Although it has been reported that there are a number of SAT-resistant logical locking methods, such as Anti-SAT blocks (ASB), that lengthen the amount of time it takes to figure out the correct key, the current methods are possibly susceptible to removal attacks based on signal probability skew (SPS) or have a high design cost. It is suggested to use an INV/BUFF key model that produces an optimized design with less overhead than XOR/XNOR. The suggested method can significantly enhance logical locking without compromising security. Moreover, it reduces the area, power, and time overheads, respectively, by 2.76 %, 12.92 %, and 12.7 % in comparison to the XOR-based technique.

The current trend to globalize the supply chain in the Integrated Circuits (ICs) industry has raised several security concerns including, among others, IC overproduction. Over the past years, logic locking has grown into a prominent countermeasure to tackle this threat in particular. Logic locking consists of “locking” an IC with an added primary input, the so-called key, which, unless fed with the correct secret value, renders the ICs unusable. One of the first criteria ensuring the quality of a logic locking technique was the output corruption, i.e., the corruption at the outputs of a locked circuit, for any wrong key value. However, since the introduction of SAT-based attacks, resulting countermeasures have compromised this criterion in favor of a better resilience against such attacks. In this work, we propose SKG-Lock+, a Provably Secure Logic Locking scheme that can thwart SAT-based attacks while maintaining significant output corruption. We perform a comprehensive security analysis of SKG-Lock+ and show its resilience against SAT-based attacks, as well as various other state-of-the-art attacks. Compared with related works, SKG-Lock+ provides higher output corruption and incurs acceptable overhead.

Logic locking is a technique that can help hinder reverse-engineering-based attacks in the IC supply chain from untrusted foundries or end-users. In 2015, the Boolean Satisfiability (SAT) attack was introduced. Although the SAT attack is effective in deobfuscating a wide range of logic locking schemes, its execution time varies widely from a few seconds to months. Previous research has shown that Graph Convolutional Networks (GCN) may be used to estimate this deobfuscation time for locked circuits with varied key sizes. In this paper, we explore whether GCN models truly understand/capture the structural/functional sources of deobfuscation hardness. In order to tackle this, we generate different curated training datasets: traditional ISCAS benchmark circuits locked with varying key sizes, as well as an important novel class of synthetic benchmarks: Substitution-Permutation Networks (SPN), which are circuit structures used to produce the most secure and efficient keyed-functions used today: block-ciphers. We then test whether a GCN trained on a traditional benchmark can predict the simple fact that a deeper SPN is superior to a wide SPN of the same size. We find that surprisingly the GCN model fails at this. We propose to overcome this limitation by proposing a set of circuit features motivated by block-cipher design principles. These features can be used as stand-alone or combined with GCN models to provide deeper topological cues than what GCNs can access.

Integrated circuits (ICs) are ubiquitous and a crucial component of electronic systems, from satellites and military hardware to consumer devices and cell phones. The computing system’s foundation of trust is the IC. Most semiconductor businesses are shifting to fabless manufacturing and outsourcing to foundries worldwide as integrated circuit feature sizes continue to decrease. That puts the design business at risk for several things, such as unauthorized overproduction, resale on the black market, and illegal copying brought on by intellectual property theft. Logic locks offer one solution in which the chip’s actual functioning is “locked” with a key only known to the inventor. The design will only function as intended if specific keys are pressed. Unlocking overproduced chips should be impossible for supply chain attackers since designers open them after manufacturing them. Logical locks against the risk of overproduction are the main subject of this research. We examine current locking systems, define features based on crucial processing, and identify commonalities and discrepancies between the employed attacker models. This research paper is intended to assist scientists, IP distributors, and SoC developers in rapidly investigating and comprehending the most recent technologies that should be considered and analyzed for additional research on logic-locking techniques.

The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. The hardware Trojans affecting a circuit’s reliability do not tend to alter the circuit layout. These Trojans often manifest as an increased delay in certain parts of the circuit. These delay faults easily escape during the integrated circuits (IC) testing phase, hence are difficult to detect. If additional patterns to detect delay faults are generated during the test pattern generation stage, then reliability attacks can be detected early without any hardware overhead. This paper proposes a novel method to generate patterns that trigger Trojans without altering the circuit model. The generated patterns’ ability to diagnose clustered Trojans are also analyzed. The proposed method uses only single fault simulation to detect clustered Trojans, thereby reducing the computational complexity. Experimental results show that the proposed algorithm has a detection ratio of 99.99% when applied on ISCAS’89, ITC’99 and IWLS’05 benchmark circuits. Experiments on clustered Trojans indicate a 46% and 34% improvement in accuracy and resolution compared to a standard Automatic Test Pattern Generator (ATPG)Tool.

PICO 算法是一个 SP 结构的迭代型轻量级密码算法, 目前对该算法的差分分析和相关密钥分析研究尚未完善. 本文借助自动化搜索技术, 设计了一套基于 SAT 方法搜索 SP 结构算法差分路径和差分闭包的自动化工具, 构建了搜索约减轮 PICO 算法差分路径以及差分闭包的 SAT 模型, 评估了 PICO 算法抵抗差分攻击的能力, 提供了比之前分析结果更准确的安全评估. 给出了 1--22 轮 PICO 算法的最优差分路径及其概率; 搜索到概率为 2−60.75 的 21 轮差分闭包和概率为 2−62.39 的 22 轮差分闭包; 实现了 26 轮 PICO 算法的密钥恢复攻击, 攻击的时间复杂度为 2101.106, 数据复杂度为 263, 存储复杂度为 263. 研究了 PICO 算法抵抗相关密钥攻击的能力, 发现 PICO 算法的密钥编排算法存在缺陷, 构建了任意轮概率为 1 的相关密钥区分器, 给出了全轮 PICO 算法的密钥恢复攻击. 所提模型适用于其他轻量级密码算法, 尤其是拥有更长的分组或者轮数更多的分组密码算法.

Cryptographic protocols form the backbone of digital society. They are concurrent multiparty communication protocols that use cryptography to achieve security goals such as confidentiality, authenticity, integrity, etc., in the presence of adversaries. Unfortunately, protocol verification still represents a critical task and a major cost to engineer attack-free security protocols. Model checking and SAT-based techniques proved quite effective in this context. This article proposes an efficient automatic model checking approach that exemplifies a security property violation. In this approach, a protocol verification is abstracted as a compact planning problem, which is efficiently solved by a state-of-the-art SAT solver. The experiments performed on some real-world cryptographic protocols succeeded in detecting new logical attacks, violating some security properties. Those attacks encompass both “type flaw” and “replay” attacks, which are difficult to tackle with the existing planning-based approaches.

PurposeTelemedicine is delivered to patient anywhere during emergency treatment care, and medical information is transferred from one site of patient to another site of specialist doctors by using mobile internet communication. Some rural areas have slow internet speed because of weak internet signal propagation from mobile towers. A good design of antenna is needed to improve mobile internet speed for big medial data transmission in telemedicine application. Hence, this paper aims to propose economically low-cost design of antenna.Design/methodology/approachTelemedicine recommended to design the satellite frequency modulation dish (SAT FMD) antenna ( where in FM radio antenna, dish antenna are combined ) to improve the internet speed at Telemedicine system and Hospitals for purpose of Telemedicine communication and information for emergency treatment.FindingsIn the proposed system, designed SAT FMD satellite-based antenna improved internet speed is achieved at 90.6% accuracy in this research method. Finding latitude and longitude angles to identify the patient location, nearest hospitals location and finding distance, shortest path routing between patient and hospital. Finding elevation, Azimuth, latitude, longitude, skew for alignment dish to focus satellite and mobile cell tower to improve internet speed at telemedicine area and hospitals and reduced transmission delay and nodal delay of big medical data.Social implicationsThe social awareness among people can be shared information of accident patient to communicate Hospital and Ambulance driver by internet mobile app tools and help find nearest hospitals to emergency treatment for accident people.Originality/valueThis paper presents SAT FMD antenna model based on satellite dish antenna consisting of FM radio receiver antenna and dish antenna for telemedicine communication.