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Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal–oxide–semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems. A 16-bit microprocessor built from over 14,000 carbon nanotube transistors may enable energy efficiency advances in electronics technologies beyond silicon.

The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the recent progress in the fabrication of complementary metal-oxide-semiconductor (CMOS) devices based on stacked 2D TMD nanoribbons and specifically highlight issues that still need to be resolved by the 2D community in five crucial research areas: contacts, channel growth, gate oxide, variability, and doping. While 2D TMD transistors have great potential, more research is needed to understand the physical interactions of 2D materials at the atomic scale. 2D semiconductors have been proposed as a potential option to replace or complement silicon electronics at the nanoscale. Here, the authors discuss the recent progress and remaining challenges that need to be addressed by the academic and industrial research communities towards the commercialization of 2D transistors.

The need for continuous size downscaling of silicon transistors is driving the industrial development of strategies to enable further footprint reduction1,2. The atomic thickness of two-dimensional materials allows the potential realization of high-area-efficiency transistor architectures. However, until now, the design of devices composed of two-dimensional materials has mimicked the basic architecture of silicon circuits3–6. Here, we report a transistor based on a two-dimensional material that can realize photoswitching logic (OR, AND) computing in a single cell. Unlike the conventional transistor working mechanism, the two-dimensional material logic transistor has two surface channels. Furthermore, the material thickness can change the logic behaviour—the architecture can be flexibly expanded to achieve in situ memory such as logic computing and data storage convergence in the same device. These devices are potentially promising candidates for the construction of new chips that can perform computing and storage with high area-efficiency and unique functions.The atomic thickness of two-dimensional materials enables the realization of a small footprint transistor architecture for photoswitching logic computing in a single cell.

Neuromorphic networks of artificial neurons and synapses can solve computationally hard problems with energy efficiencies unattainable for von Neumann architectures. For image processing, silicon neuromorphic processors outperform graphic processing units in energy efficiency by a large margin, but deliver much lower chip-scale throughput. The performance-efficiency dilemma for silicon processors may not be overcome by Moore’s law scaling of silicon transistors. Scalable and biomimetic active memristor neurons and passive memristor synapses form a self-sufficient basis for a transistorless neural network. However, previous demonstrations of memristor neurons only showed simple integrate-and-fire behaviors and did not reveal the rich dynamics and computational complexity of biological neurons. Here we report that neurons built with nanoscale vanadium dioxide active memristors possess all three classes of excitability and most of the known biological neuronal dynamics, and are intrinsically stochastic. With the favorable size and power scaling, there is a path toward an all-memristor neuromorphic cortical computer. The neuromorphic computing based on complementary metal-oxide-semiconductor transistors holds promise for artificial intelligence, but it suffers from the trade-off between scalability and biological fidelity. Yi et al. emulate 23 types of biological neuronal behaviors using scalable VO 2 active memristors.

Aligned semiconducting carbon nanotubes are a potential alternative to silicon in the creation of scaled field-effect transistors (FETs) due to their easy miniaturization and high energy efficiency. However, it remains unclear whether aligned nanotube transistors can be fabricated at the same dimensions as low-node silicon technology and maintaining high performance. Here we report aligned carbon nanotube FETs that can be scaled to a size corresponding to the 10 nm silicon technology node. We first fabricate nanotube FETs with a contacted gate pitch of 175 nm (achieved by scaling the gate length and contact length to 85 nm and 80 nm, respectively) that exhibit an on current of 2.24 mA μm –1 and peak transconductance of 1.64 mS μm –1 ; this is superior to 45 nm silicon technology node transistors in terms of size and electronic performance. Six nanotube FETs are used to create a static random-access memory cell with an area of 0.976 μm 2 , which is comparable with the 90 nm silicon technology node. A full-contact structure is then introduced between the metal and nanotubes to achieve a low contact resistance of 90 Ω μm and reduce the dependence on the contact length. This is used to create nanotube FETs with a contacted gate pitch of 55 nm—corresponding to the 10 nm node—with carrier mobility and Fermi velocity higher than the 10 nm silicon metal–oxide–semiconductor transistors. Aligned carbon nanotubes can be used to create six-transistor static random-access memory cells with an area of less than 1 μm 2 and performance superior to cells made using 90-nm-node silicon transistors, as well as field-effect transistors with scaled contacted gate pitch comparable with the 10 nm silicon technology node.

An erbium-doped silicon transistor prepared by ion implantation and co-doped with oxygen is investigated by photocurrent generation in the telecommunication range. The photocurrent is explored at room temperature as a function of the wavelength by using a supercontinuum laser source working in the μW range. The 1-μm2 transistor is tuned to involve in the transport only those electrons lying in the Er-O states. The spectrally resolved photocurrent is characterized by the typical absorption line of erbium and the linear dependence of the signal over the impinging power demonstrates that the Er-doped transistor is operating far from saturation. The relatively small number of estimated photoexcited atoms (≈ 4 × 10 4 ) makes Er-dpoed silicon potentially suitable for designing resonance-based frequency selective single photon detectors at 1550 nm.

Two-dimensional semiconductors such as layered transition metal dichalcogenides can offer superior immunity to short-channel effects compared with bulk semiconductors such as silicon. As a result, these materials can be used to create highly scaled transistors. However, on-state current densities of two-dimensional semiconductor transistors are still below those of silicon transistors. Here we show that bilayer tungsten diselenide transistors that have channel lengths of less than 100 nm can exhibit on-state current densities above 1.0 mA μm −1 and on-state resistances below 1.0 kΩ μm at room temperature. The devices have atomically clean van der Waals vanadium diselenide contacts and are created using van der Waals epitaxy and controlled crack formation processes. With a 20-nm-long and 1.3-nm-thick transistor, an on-state current density of 1.72 mA μm −1 and on-state resistance of 0.50 kΩ μm are achieved, showing comparable performance to silicon transistors with similar channel lengths and driving voltages. Vanadium diselenide van der Waals contacts made with a controlled crack formation process can be used to fabricate tungsten diselenide transistors with channel lengths of less than 100 nm, on-state current densities of up to 1.7 mA μm –1 and on-state resistances down to 0.50 kΩ μm.

Selector devices are indispensable components of large-scale nonvolatile memory and neuromorphic array systems. Besides the conventional silicon transistor, two-terminal ovonic threshold switching device with much higher scalability is currently the most industrially favored selector technology. However, current ovonic threshold switching devices rely heavily on intricate control of material stoichiometry and generally suffer from toxic and complex dopants. Here, we report on a selector with a large drive current density of 34 MA cm −2 and a ~10 6 high nonlinearity, realized in an environment-friendly and earth-abundant sulfide binary semiconductor, GeS. Both experiments and first-principles calculations reveal Ge pyramid-dominated network and high density of near-valence band trap states in amorphous GeS. The high-drive current capacity is associated with the strong Ge-S covalency and the high nonlinearity could arise from the synergy of the mid-gap traps assisted electronic transition and local Ge-Ge chain growth as well as locally enhanced bond alignment under high electric field. Designing efficient selector devices for large-scale nonvolatile memory and neuromorphic array systems remains a challenge. Here, the authors propose a two-terminal ovonic threshold switching selector device with a large drive current density and a high nonlinearity, capable emulating stochastic integrate-and-fire neuron behavior.

Taking aim at silicon Silicon transistors in microelectronics are shrinking to close to the size at which quantum effects begin to have an impact on device performance. As silicon looks certain to remain the semiconductor material of choice for a while yet, such effects may be turned into an advantage by designing silicon devices that can process quantum information. One approach is to make use of electron spins generated by phosphorus dopant atoms buried in silicon, as they are known to represent well-isolated quantum bits (qubits) with long coherence times. It has not been possible to control single electrons in silicon with the precision for qubits, but now Andrea Morello and colleagues report single-shot, time-resolved readout of electron spins in silicon. This is achieved by placing the phosphorus donor atoms near a charge-sensing device called a single-electron transistor, which is fully compatible with current microelectronic technology. The demonstrated high-fidelity single-shot spin readout opens a path to the development of a new generation of quantum computing and spintronic devices in silicon. Electron spins generated by phosphorus dopant atoms buried in silicon represent well-isolated quantum bits with long coherence times, but so far the control of such single electrons has been insufficient to use them in this way. These authors report single-shot, time-resolved readout of electron spins in silicon, achieved by coupling the donor atoms to a charge-sensing device called a single-electron transistor. This opens a path to the development of a new generation of quantum computing and spintronic devices in silicon. The size of silicon transistors used in microelectronic devices is shrinking to the level at which quantum effects become important 1 . Although this presents a significant challenge for the further scaling of microprocessors, it provides the potential for radical innovations in the form of spin-based quantum computers 2 , 3 , 4 and spintronic devices 5 . An electron spin in silicon can represent a well-isolated quantum bit with long coherence times 6 because of the weak spin–orbit coupling 7 and the possibility of eliminating nuclear spins from the bulk crystal 8 . However, the control of single electrons in silicon has proved challenging, and so far the observation and manipulation of a single spin has been impossible. Here we report the demonstration of single-shot, time-resolved readout of an electron spin in silicon. This has been performed in a device consisting of implanted phosphorus donors 9 coupled to a metal-oxide-semiconductor single-electron transistor 10 , 11 —compatible with current microelectronic technology. We observed a spin lifetime of ∼6 seconds at a magnetic field of 1.5 tesla, and achieved a spin readout fidelity better than 90 per cent. High-fidelity single-shot spin readout in silicon opens the way to the development of a new generation of quantum computing and spintronic devices, built using the most important material in the semiconductor industry.

In-memory computing architectures based on memristive crossbar arrays could offer higher computing efficiency than traditional hardware in deep learning applications. However, the core memory devices must be capable of performing high-speed and symmetric analogue programming with small variability. They should also be compatible with silicon technology and scalable to nanometre-sized footprints. Here we report an electrochemical synaptic transistor that operates by shuffling protons between a hydrogenated tungsten oxide channel and gate through a zirconium dioxide protonic electrolyte. These devices offer multistate and symmetric programming of channel conductance via gate-voltage pulse control and small cycle-to-cycle variation. They can be programmed at frequencies approaching the megahertz range and exhibit endurances of over 100 million read–write cycles. They are also compatible with complementary metal–oxide–semiconductor technology and can be scaled to lateral dimensions of 150 × 150 nm 2 . Through monolithic integration with silicon transistors, we show that pseudo-crossbar arrays can be created for area- and energy-efficient deep learning accelerator applications. Oxide-based solid-state protonic electrochemical transistors that have symmetric operation and are compatible with CMOS technology can be used to create crossbar arrays for deep learning applications.