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In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions.

As semiconductor technologies advance, SRAM cells deployed in space systems face heightened sensitivity to radiation-induced soft errors. In conventional 6T SRAM, when high-energy particles strike sensitive nodes, single-event upsets (SEUs) may occur, flipping stored bits. Furthermore, with aggressive scaling, charge sharing among adjacent devices can trigger single-event multi-node upsets (SEMNU). To address these reliability concerns, this study presents a radiation-hardened SRAM design, SHWA18T, tailored for space applications. The proposed architecture is evaluated against IASE16T, PRO14T, PRO16T, QCCS, SIRI, and SEA14T. Simulation analysis demonstrates that SHWA18T achieves improved performance, particularly in terms of critical charge and write capability. The design was implemented in 90 nm CMOS technology at a 1 V supply. With enhanced robustness, the cell withstands both SEUs and SEMNUs, thereby guaranteeing stable data retention in space environments.

Single event upsets (SEUs), which are caused by radiation particles, have emerged as a significant concern in aircraft applications. Soft mistakes, which manifest as corruption of data in memory chips and circuit faults, are mostly produced by SEUs. The utilization of SEUs can have both advantageous and detrimental effects in some critical memory applications. Nevertheless, in adherence to design principles, Radiation-Hardening-By-Design (RHBD) methodologies have been employed to mitigate the impact of soft mistakes in memory. This study presents a novel memory cell design, referred to as a Robust 10T memory cell, which aims to improve dependability in the context of aerospace radiation environments. The proposed design has several advantages, including reduced area, low power consumption, good stability, and a decreased number of transistors. Simulations were conducted using the TSMC 65nm CMO technology, employing the Tanner tool. The parameters of the RHB 10T cell were measured and afterwards compared to those of the 12T memory cell. The findings obtained from the simulation demonstrate that the performance of the 10T memory cell surpasses that of the 12T memory cell.

Radiation induced soft errors impact memory circuits and their response gets transposed or disturbed which makes it crucial to protect the memory unit. Radiation-immune memory devices have extensive applications in space, biomedical, smart devices, and wearable devices. A radiation hardened by design circuit using Dual Interlocked Storage Cell (DICE) is implemented with varied transistor sizing to propose the design that has optimum performance and minimum power dissipation. The design is tested for Single Event Upsets using the double exponential current model for current source of maximum amplitude 1 A. The proposed design is validated using Cadence Virtuoso version IC 6.1.5 at 180 nm CMOS technology node with variation of ± 10% of V DD = 1.8 V. The sensitivity of the circuit to process, voltage and temperature variations are shown with the help of Monte Carlo simulations. Various iterations performed during simulations make the proposed circuit suitable for use in critical applications.

This paper presents a comprehensive register transfer-level (RTL) fault injection study targeting the program counter (PC) of the LEON3 processor, a SPARC V8-compliant core widely used in safety-critical and radiation-prone embedded applications. Using the enhanced NETFI+ framework, over four million faults, including single-event upsets (SEUs), multiple-bit upsets (MBUs), and single-event transients (SETs), were systematically injected into the PC across all pipeline stages. The analysis reveals that early stages, particularly Fetch (FE), Decode (DE), Register Access (RA), and Execute (EX), are highly sensitive to SEU and MBU faults. The propagation of errors detected in the two early stages of the pipeline (FE and DE) is classified with an important percentage of halt execution and timeout traps. Intermediate stages, such as RA and EX, exhibited a higher incidence of silent data corruption and halt execution, while the Memory (ME) and Exception (XC) stages demonstrated greater resilience through fault masking. SET faults were mostly transient and masked, though they occasionally resulted in control flow anomalies. In addition to error classification, detailed trap and exception analysis was performed to characterize fault-induced failure mechanisms. The findings underscore the need for pipeline-stage-specific hardening strategies and highlight the value of simulation-based fault injection for early design validation in safety-critical embedded processors.

Reconfigurable hardware, extensively employed in mission-critical digital applications like space and military electronics due to its adaptability, encounters the issue of soft errors, especially in control path elements, which could result in functional failure. Various system-level fault tolerance methodologies exist, and this paper implements a bio-inspired fault tolerance technique called evolvable hardware (EHW). The preferred implementation of the EHW system involves hosting the evolutionary algorithm on the processor alongside the reconfigurable hardware. However, this approach encounters delays in the intercommunication of the evolved circuit between the reconfigurable hardware and the processor. To address this issue, the paper proposes a two-tier architecture to achieve absolute fault mitigation in the controller. In this architecture, Tier-1 involves the digital implementation of the genetic algorithm on the reconfigurable hardware to mitigate errors in the controller, while Tier-2 focuses on mitigating errors occurring in Tier-1. The aim is to establish an absolute and self-resilient controller hardware to mitigate faults. The study simulates faults at the target circuit and genetic module as a proof of concept. The proposed two-tier single event upset (SEU) mitigation is deployed on Microsemi’s ProAsic3e FPGA (Field Programmable Gate Array), achieving an average efficiency of 91%. This efficiency is accompanied by ten times lesser resource utilization compared to traditional methodologies and a 30% accelerated speed when compared to hybrid evolvable systems.

To meet the high-reliability requirements of real-time on-orbit tasks, this paper proposes a fault-tolerant reinforcement design method for spaceborne intelligent processing algorithms based on convolutional neural networks (CNNs). This method is built on a CNN accelerator using Field-Programmable Gate Array (FPGA) technology, analyzing the impact of Single-Event Upsets (SEUs) on neural network computation. The accelerator design integrates data validation, Triple Modular Redundancy (TMR), and other techniques, optimizing a partial fault-tolerant architecture based on SEU sensitivity. This fault-tolerant architecture analyzes the hardware accelerator, parameter storage, and actual computation, employing data validation to reinforce model parameters and spatial and temporal TMR to reinforce accelerator computations. Using the ResNet18 model, fault tolerance performance tests were conducted by simulating SEUs. Compared to the prototype network, this fault-tolerant design method increases tolerance to SEU error accumulation by five times while increasing resource consumption by less than 15%, making it more suitable for spaceborne on-orbit applications than traditional fault-tolerant design approaches.

Random Access Memory (RAM) refers to the main memory of a computer. For the central processor unit (CPU) to operate quickly and effectively, it stores operating system software, applications, and other data. Unfortunately, single event upset and other high-soft error problems plague standard static RAM (SRAMs) in aircraft applications (SEU). Many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD), such as the 12T We-Quatro and twelve-transistor (12T) Dice SRAM cells, have been created to address the soft error issues. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 × 32 array architecture. The power consumption of a 32 × 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 × 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology file is used to simulate the comparative analysis for the SRAM cell.

This paper presents a radiation-hardened 4-bit flash analog-to-digital converter (ADC) implemented in a 22 nm fully depleted silicon-on-insulator (FD-SOI) process for high-reliability applications in radiation environments. To improve single-event upsets (SEU) tolerance, the design introduces a compact fault-tolerant logic scheme based on Dual Modular Redundancy (DMR), offering reliability comparable to Triple Modular Redundancy (TMR) while using two storage nodes instead of three, and a simple XOR-based check in place of a majority voter. A distributed sampling architecture mitigates SEU vulnerabilities in the input path, while thin-oxide devices are used in analog-critical circuits to enhance total ionizing dose (TID) resilience. Post-layout simulations demonstrate SEU detection within 200 ps and correction within ~600 ps. The ADC achieves an active area of 0.089 mm2, power consumption below 30 µW, and provides a scalable solution for radiation-tolerant data acquisition in aerospace and other high-reliability systems.

In application domains where severe environmental conditions are unavoidable, including high-energy physics and nuclear power plants, accurate and dependable time-to-digital converters (TDCs) are essential components. Single-event upsets (SEUs) associated with the configuration memory of field-programmable gate array (FPGA)-based implementations are becoming common sources of performance degradation even in terrestrial areas. Hence, the need to test and mitigate the effects of SEUs on FPGA-based TDCs is crucial to ensure that the design achieves reliable performance under critical conditions. The TMR SEM IP provides real-time fault injection, and dynamic SEU monitoring and correction in safety critical conditions without intervening with the functionality of the system, unlike traditional fault injection methods. This paper presents a scalable and fast fault emulation framework that tests the effects of SEUs on the configuration memory of a 5.7 ps-resolution TDC implemented on ZedBoard. The experimental results demonstrate that the standard deviation in mean bin width is 2.4964 ps for the golden TDC, but a 0.8% degradation in the deviation is observed when 3 million SEUs are injected, which corresponds to a 0.02 ps increment. Moreover, as the number of SEUs increases, the degradation in the RMS integral non-linearity (INL) of the TDC also increases, which shows 0.04 LSB (6.8%) and 0.05 LSB (8.8%) increments for 1 million and 3 million SEUs injected, respectively. The RMS differential non-linearity (DNL) of the faulty TDC with 3 million SEUs injected shows a 0.035 LSB (0.8%) increase compared to the golden TDC.