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Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) of modern computing systems. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Researchers have proposed a variety of FA cells with diverse design techniques, each having its pros and cons. As a result, a systematic method for performance comparison of FA cells using a common simulation platform has become necessary. In this work, we present an extensive study of FA cells. We have compared the performance of thirty-three (33) existing 1-bit FA cells. The drive powers of these FA cells have been compared by applying a variety of load conditions. In addition, the 1-bit FA cells have been extended to 32-bit structures to test their scalability and to investigate their performance in wide-word structures. We have determined that twenty-one (21) of the thirty-three (33) FA cells cannot operate in a 32-bit structure, even though some of them exhibit excellent performance as a 1-bit cell. The main finding of this research is that the single-bit performance parameters of FA cells should not be considered as the main basis for performance comparison. Any FA cell should be analyzed in a multi-bit structure to determine its practical effectiveness. Article Highlights Hybrid full adders offer better performance than single logic full adders Many existing full adder cells are not scalable Conventional Mirror CMOS full adder offers better performance than many recent full adders in wide adder structure

In the literature, it is well known that reactive power management is the greatest challenge in wind turbine based on a three-phase self-excited induction generator. Any variation of wind speed or load causes a variation on the needed reactive power and thus a voltage fluctuation. Flexible AC transmission device such as STATCOM become then a necessity to prevent voltage instability and hence voltage collapse at the point of common coupling. This paper proposes so a new control strategy for voltage regulation of an asynchronous wind turbine based on a combination of a single input fuzzy logic regulator and a sliding mode controller. Compared to the classical control strategy with PI regulators, the performance of the proposed compensator has been significantly improved when it is controlled by the new approach and the system have shown more robustness and stability regarding external disturbances. The present document traits so the modelling of the power system, the simulation results and the controller’s scheme and design.

This paper describes a control scheme that provides an efficient way to design a Fuzzy Logic Controller (FLC) for the unmanned underwater vehicle (UUV). The proposed method, known as the Single Input Fuzzy Logic Controller (SIFLC), reduces the conventional two-input FLC (CFLC) to a single input single output (SISO) controller. The SIFLC offers significant reduction in rule inferences and simplify the tuning of control parameters. Practically it can be easily implemented by a look-up table using a low cost microprocessor due its piecewise linear control surface. To verify its effectiveness, the control algorithm is simulated using the Marine Systems Simulator (MSS) on the Matlab/Simulink® platform. The result indicates that both the SIFLC and CFLC give identical response to the same input sets. However SIFLC requires very minimum tuning effort and its execution time is in the orders of two magnitudes less than CFLC.

In this paper, a heating and ventilation model VVS-400 from Instrutek, Larvik, Norway is modeled using ARX model structure and linear black-box technique. The conventional PID controller and artificial Fuzzy controller are designed based on the approximated plant model and real plant model. The approximated plant model is estimated using System Identification approach while the real plant model is developed by interfacing the Real-time Windows Target toolbox in Matlab with real VVS-plant by using data acquisition (DAQ) card PCI-1711. An artificial Fuzzy controller approach is incorporated in two ways which are conventional Fuzzy logic controller (FLC) and a replacement of conventional fuzzy controller known as Single input fuzzy logic controller (SIFLC). Simulations and experiment validate the equivalency of both controllers. Results reveal that SIFLC found to be better than FLC due to its less computation time compared to conventional FLC.

The three-dimensional (3D) model of a feedforward neural network(NN) based on so called N-hypercube topology isproposed. The N-hypercube is different from theclassical hypercube used in communication theory, and in Booleanalgebra. This new structure has been created based on a novelalgorithm for embedding a binary decision tree and binary decisiondiagram into a N-hypercube. It is shown thatN-hypercube topology is a reasonable solution toimplement NN of threshold gates, in particular, on thesingle-electron devices. The 3D design methodology of feedforwardNN is oriented to technology mapping to nanodevices. Results ofextensive experimental study of feedforward networks consistingof over 3500 N-hypercubes are presented.

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static‐to‐dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state‐of‐the‐art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS‐like, SDCVSL, and pseudo N‐type, respectively, in terms of energy consumption.

Powerful information processing and ubiquitous computing are crucial for all machines and living organisms. The Watson-Crick base-pairing principle endows DNA with excellent recognition and assembly abilities, which facilitates the design of DNA computers for achieving intelligent systems. However, current DNA computational systems are always constrained by poor integration efficiency, complicated device structures or limited computational functions. Here, we show a DNA arithmetic logic unit (ALU) consisting of elemental DNA logic gates using polymerase-mediated strand displacement. The use of an enzyme resulted in highly efficient logic gates suitable for multiple and cascaded computation. Based on our basic single-rail DNA configuration, additional combined logic gates (e.g., a full adder and a 4:1 multiplexer) have been constructed. Finally, we integrate the gates and assemble the crucial ALU. Our strategy provides a facile strategy for assembling a large-scale complex DNA computer system, highlighting the great potential for programming the molecular behaviors of complicated biosystems. Current DNA computational systems are constrained by integration efficiency, device structures and limited functions. Here the authors design a DNA arithmetic logic unit that uses polymerase-mediated strand displacement.

Biological organisms perform complex information processing and control tasks using sophisticated biochemical circuits, yet the engineering of such circuits remains ineffective compared with that of electronic circuits. To systematically create complex yet reliable circuits, electrical engineers use digital logic, wherein gates and subcircuits are composed modularly and signal restoration prevents signal degradation. We report the design and experimental implementation of DNA-based digital logic circuits. We demonstrate AND, OR, and NOT gates, signal restoration, amplification, feedback, and cascading. Gate design and circuit construction is modular. The gates use single-stranded nucleic acids as inputs and outputs, and the mechanism relies exclusively on sequence recognition and strand displacement. Biological nucleic acids such as microRNAs can serve as inputs, suggesting applications in biotechnology and bioengineering.

This work aims to present a novel energy-efficient single transistor leaky integrate-and-fire neuron for future neuromorphic computing. It comprises of a SiGe-based MOSFET, having channel length of 400 nm. Using 2D simulation, it has been verified that the proposed SiGe-based single transistor neuron accurately mimics the spiking behavior of the biological neuron, while eliminating the need of external circuitry and exorbitant energy consumption. The neuron consumes energy of 3.8 pJ/spike, which is 11.8 times and 2.1 times lesser than the previously proposed Si-based and Ge-based single transistor neurons, respectively. It also shows improvement in terms of controllability, simplicity, integration density, and fabrication process. By designing threshold logic gates, the proposed neuron has been employed to implement universal digital logic functions, such as NAND and NOR. Finally, the recognition ability for MNIST handwritten digits has been verified. It has been confirmed that besides imitating the neuronal behavior accurately, the proposed neuron can also be used in practical spiking neural networks for image classification with an accuracy of 93.79%.