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In the last few decades, industrial sectors such as smart manufacturing and aerospace have rapidly developed, contributing to the increase in production of more complex electronic boards based on SMT (Surface Mount Technology). The assembly phases in manufacturing these electronic products require the availability of technological solutions able to deal with many heterogeneous products and components. The small batch production and pre-production are often executed manually or with semi-automated stations. The commercial automated machines currently available offer high performance, but they are highly rigid. Therefore, a great effort is needed to obtain machines and devices with improved reconfigurability and flexibility for minimizing the set-up time and processing the high heterogeneity of components. These high-level objectives can be achieved acting in different ways. Indeed, a work station can be seen as a set of devices able to interact and cooperate to perform a specific task. Therefore, the reconfigurability of a work station can be achieved through reconfigurable and flexible devices and their hardware and software integration and control For this reason, significant efforts should be focused on the conception and development of innovative devices to cope with the continuous downscaling and increasing variety of the products in this growing field. In this context, this paper presents the design and development of a multi-mode hybrid micro-gripper devoted to manipulate and assemble a wide range of micro- and meso-SMT components with different dimensions and proprieties. It exploits two different handling technologies: the vacuum and friction.

The automated optical inspection of a surface mount technology line inspects a printed circuit board for quality assurance, and subsequently classifies the chip assembly defects. However, it is difficult to improve the accuracy of previous defect classification methods using full chip component images with single-stream convolutional neural networks due to interference elements such as silk lines included in a printed circuit board image. This paper proposes a late-merge dual-stream convolutional neural network to increase the classification accuracy. Two solder regions are extracted from a printed circuit board image and are input to a convolutional neural network with a merge stage. A new convolutional neural network structure is then proposed that is able to classify for defects. Since defect features are concentrated in solder regions, the classification accuracy is increased. In addition, the network weight is reduced due to a reduction of the input data. Experimental results for the proposed method show a 5.3% higher performance in F1-score than a single-stream convolutional neural network based on full chip component images.

Surface mount technology (SMT) plays an important role in integrated circuits, but due to thermal stress alternation caused by temperature cycling, it tends to have thermo-mechanical reliability problems. At the same time, considering the environmental and health problems of lead (Pb)-based solders, the electronics industry has turned to lead-free solders, such as ternary alloy Sn-3Ag-0.5Cu (SAC305). As lead-free solders exhibit visco-plastic mechanical properties significantly affected by temperature, their thermo-mechanical reliability has received considerable attention. In this study, the interface delamination of an SMT solder joint using a SAC305 alloy under temperature cycling has been analyzed by the nonlinear finite element method. The results indicate that the highest contact pressure at the four corners of the termination/solder horizontal interface means that delamination is most likely to occur, followed by the y-direction side region of the solder/land interface and the top arc region of the termination/solder vertical interface. It should be noted that in order to keep the shape of the solder joint in the finite element model consistent with the actual situation after the reflow process, a minimum energy-based morphology evolution method has been incorporated into the established finite element model. Eventually, an Improved Efficient Global Optimization (IEGO) method was used to optimize the geometry of the SMT solder joint in order to reduce the contact pressure at critical points and critical regions. The optimization result shows that the contact pressure at the critical points and at the critical regions decreases significantly, which also means that the probability of thermal-induced delamination decreases.

Surface-mount technology (SMT) is the technology used in the production of printed circuit boards (PCB) plays a vital role in PCB manufacturing for applications ranging from communication devices to medical systems. A significant challenge in the stencil printing process, a critical step in PCB production, is solder paste buildup in stencil apertures, contributing to 57%–71% of soldering defects. To address this issue, this study presents a convolutional neural network (CNN)-based framework for categorizing solder paste residue levels into three classes: low, moderate, and high. The methodology involves cropping and pre-processing images of stencil apertures, which are then fed into the CNN model for classification. To enhance model robustness and prevent overfitting, data augmentation techniques, including aperture rotation, are applied, effectively increasing the dataset size and promoting generalization. The model achieves a classification accuracy of 87% during testing, with precision and recall values provided for each residue class. This approach aims to optimize the stencil printing process by enabling accurate residue categorization and facilitating targeted cleaning cycles, ultimately reducing soldering defects and improving PCB production efficiency.

Purpose This paper aims to discuss the key factors affecting the quality characteristics, such as the number of solder balls, the spread distance of residual underfill and the completion time of the underfilling. Design/methodology/approach The Taguchi method is applied to configure the orthogonal table and schedule and execute the experiment. In addition, principal components analysis is used to obtain the points. Then, based on gray relational analysis and the technique for order preference by similarity to ideal solution, the closeness between each quality characteristic and the ideal solution is adopted as the basis for evaluating the quality characteristics. Findings The optimal parameter combination is proposed, which includes 4 dispensing (11 mg/dispensing), a “half flow” interval state, 80°C preheating module PCB board and an L-shaped dispensing path and verification testing is performed. Originality/value For vehicles and handheld electronic products, solder joints that connect electronic components to printed circuit boards may be cracked due to collision, vibration or falling. Consequently, solder balls are closely surrounded and protected by the underfill to improve joint strength and resist external force factors, such as collision and vibration. This paper addresses the defects caused during the second reflow process of a vehicle electronic communication module after the underfilling process.

This special issue of SSMT brings together seven papers demonstrating the latest achievements in the applications of computational modelling technology to soldering processes and solder joint reliability. Why use computational models? The performance of soldering materials during product assembly is governed by complex interacting physical phenomena.

Purpose Low relative humidity (RH) effect surface mount devices in numerous ways. The smaller size (0201) capacitor and resistor start wasting when RH is low. Due to low RH, electrostatic charges built-up on the surface of surface mount devices (SMDs) and component’s reel. The positive charged SMDs stick with the negatively charged reel tape and are wasted. This paper comprehensively explores the environmental effects on 0201 size surface mount devices during mounting process. Different type and size of surface mount devices are tested in low and desired RH to validate the effectiveness of the proposed approach. This paper will also highlight high electrostatic discharge (ESD) due to low RH which can be detrimental for small size surface mount devices. The experimental and graphical illustrations will stipulate the results of success rate for mounting components. The effect on ESD, subsequently varying temperature and humidity will also be analyzed. Design/methodology/approach In this paper, 0201 SDMs will be considered for analysis. The surface mount technology (SMT) plant temperature and humidity has been varied to examine the properties of small size SMDs. Total 5 hours production data are collected from Laptop motherboard production environment. This approach is applicable to all SMT environment. Findings The authors reduced the wastage of 0201 chip size resistor and capacitor. Total 11 components are selected of this size, and there success rate is observed during mounting. These components are first observed in harsh environment where the temperature is first set to 20ºC and RH is set to 25 per cent. The success rate of these components is very low due to component’s wastage. When the plant temperature is set to 25ºC and RH is set to 45 per cent, the success rate of mounting increased up to 100 per cent. A single component placement success rate with respect to RH is observed for one month. The results are shown in Table IV. It can be seen that the success rate is near 100 per cent when RH and temperature is maintained in production environment. To eliminate the ESD build-up in material and equipment in manufacturing environment humidification is a very effective way. When the RH is kept to 45 per cent, the moisture content of the air is a natural conductor and earths any ESD in environment. Originality/value Experimental data have been obtained from Laptop motherboard manufacturing process to validate the effectiveness of proposed approach.

Conventional rigid electronic systems use a number of metallization layers to route all necessary connections to and from isolated surface mount devices using well-established printed circuit board technology. In contrast, present solutions to prepare stretchable electronic systems are typically confined to a single stretchable metallization layer. Crossovers and vertical interconnect accesses remain challenging; consequently, no reliable stretchable printed circuit board (SPCB) method has established. This article reports an industry compatible SPCB manufacturing method that enables multilayer crossovers and vertical interconnect accesses to interconnect isolated devices within an elastomeric matrix. As a demonstration, a stretchable (260%) active matrix with integrated electronic and optoelectronic surface mount devices is shown that can deform reversibly into various 3D shapes including hemispherical, conical or pyramid. To realize multilayer stretchable printed circuit boards (SPCBs), advancements in industrially-viable materials and processing methods are required. Here, the authors report multilayer SPCBs with electrical wiring capable of interconnecting isolated devices in different layers within an elastomeric matrix.

Distributed micro‐energy harvesting devices offer the flexibility, sustainability, and multi‐scenario applicability that will be critical to wearable electronic products in the Internet of Things. The radiofrequency and triboelectric (RF‐TE) hybrid energy harvester (HEH) concept and prototype is presented for the first time, to simultaneously capture the energy from ambient electromagnetic waves and biological motions. The proposed hybrid energy harvesting system consists of a wearable rectenna, a triboelectric nanogenerator (TENG), and a power management circuit (PMC). Among them, the all‐fabric rectenna exhibits good impedance matching characteristics in the ISM frequency. The flexible TENG unit can generate a maximum power density of 0.024 µW cm−2. The designed multifunctional fabric‐based PMC can considerably enhance the controllability of harvested hybrid energy. Additionally, a normalizable fabric circuit board quasi surface mount technology (FCB‐SMT) is proposed to integrate all modules on the same fabric substrate in one step, making the entire system superior mechanical robustness. The proposed wearable fabric‐based RF‐TE hybrid energy harvester is capable of successfully driving consumer electronics (such as sensors, watches, etc.). It provides a new energy solution strategy for self‐powered wearable electronic devices and is anticipated to encourage the efficient utilization of renewable energy. A novel flexible and wearable hybrid energy harvesting strategy is developed. The system consists of a rectenna, a triboelectric nanogenerator (TENG), and a power management circuit (PMC). An effective fabric circuit board quasi surface mount technology (FCB‐SMT) is proposed for realizing the all‐fabric hybrid energy harvester. This research could benefit the development of self‐powered wearable devices.

The creep model is the main form of rock model used to describe the rheological behavior of rocks. A large number of creep models have been proposed, but many are complicated and/or are not able to fully simulate the three stages of rock creep. Hence, an important focus of research on rock creep has been to develop a model with few parameters and better simulation performance. To achieve this, in this study, we propose a new four-element creep model, based on variable-order fractional derivatives and continuum damage mechanics. The newly proposed creep model agrees well with experimental data for Changshan rock salt. The results show that the segmentation treatment is an effective approach for simulating the creep behavior of rocks.