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A functional, human, multiorgan, pumpless, immune system‐on‐a‐chip featuring recirculating THP‐1 immune cells with cardiomyocytes, skeletal muscle, and liver in separate compartments in a serum‐free medium is developed. This in vitro platform can emulate both a targeted immune response to tissue‐specific damage, and holistic proinflammatory immune response to proinflammatory compound exposure. The targeted response features fluorescently labeled THP‐1 monocytes selectively infiltrating into an amiodarone‐damaged cardiac module and changes in contractile force measurements without immune‐activated damage to the other organ modules. In contrast to the targeted immune response, general proinflammatory treatment of immune human‐on‐a‐chip systems with lipopolysaccharide (LPS) and interferon‐γ (IFN‐γ) causes nonselective damage to cells in all three‐organ compartments. Biomarker analysis indicates upregulation of the proinflammation cytokines TNF‐α, IL‐6, IL‐10, MIP‐1, MCP‐1, and RANTES in response to LPS + IFN‐γ treatment indicative of the M1 macrophage phenotype, whereas amiodarone treatment only leads to an increase in the restorative cytokine IL‐6 which is a marker for the M2 phenotype. This system can be used as an alternative to humanized animal models to determine direct immunological effects of biological therapeutics including monoclonal antibodies, vaccines, and gene therapies, and the indirect effects caused by cytokine release from target tissues in response to a drug's pharmacokinetics (PK)/pharmacodynamics (PD) profile. A functional, human, multiorgan, pumpless, immune system‐on‐a‐chip containing recirculating THP‐1 immune cells with cardiomyocytes, skeletal muscle, and liver compartments with a serum‐free medium is developed. This system emulates both a targeted immune response to tissue‐specific damage and a holistic immune response to proinflammatory compound exposure. These immune responses are reflected in changes to parenchymal cell functionality and cytokine release.

Understanding the immune system is of great importance for the development of drugs and the design of medical implants. Traditionally, two-dimensional static cultures have been used to investigate the immune system in vitro, while animal models have been used to study the immune system’s function and behavior in vivo. However, these conventional models do not fully emulate the complexity of the human immune system or the human in vivo microenvironment. Consequently, many promising preclinical findings have not been reproduced in human clinical trials. Organ-on-a-chip platforms can provide a solution to bridge this gap by offering human micro-(patho)physiological systems in which the immune system can be studied. This review provides an overview of the existing immune-organs-on-a-chip platforms, with a special emphasis on interorgan communication. In addition, future challenges to develop a comprehensive immune system-on-chip model are discussed.

The utilization of unlabeled electrocardiogram (ECG) data is always a critical topic in artificial intelligence healthcare, as the manual annotation for ECG data is a time-consuming task that requires much medical expertise. The recent development of self-supervised learning, especially contrastive learning, has provided helpful inspirations to solve this problem. In this paper, a joint cross-dimensional contrastive learning algorithm for unlabeled 12-lead ECGs is proposed. Unlike existing studies about ECG contrastive learning, our algorithm can simultaneously exploit unlabeled 1-dimensional ECG signals and 2-dimensional ECG images. A cross-dimensional contrastive learning method enhances the interaction between 1-dimensional and 2-dimensional ECG data, resulting in a more effective self-supervised feature learning. Combining this cross-dimensional contrastive learning, a 1-dimensional contrastive learning with ECG-specific transformations is employed to constitute a joint model. To pre-train this joint model, a new hybrid contrastive loss balances the 2 algorithms and uniformly describes the pre-training target. In the downstream classification task, the features learned by our algorithm shows impressive advantages. Compared with other representative methods, it achieves a at least 5.99% increase in accuracy. For real-world applications, an efficient heterogenous deployment on a “system-on-a-chip” (SoC) is designed. According to our experiments, the model can process 12-lead ECGs in real-time on the SoC. Furthermore, this heterogenous deployment can achieve a 14 × faster inference than the pure software deployment on the same SoC. In summary, our algorithm is a good choice for unlabeled 12-lead ECG utilization, the proposed heterogenous deployment makes it more practical in real-world applications. •A cross-dimensional (CD) contrastive learning combines 1-D and 2-D ECG data.•Fusion of 1-D and CD contrastive learning improves downstream performance.•Heterogeneous deployment on SoC helps accelerate inference by 14 × .•The system has a good potential for home-based healthcare using ECG.

The circuit design in the system on a chip (SoC) is very difficult task during the physical design of a chip. Considering the fact of increasing complexity in the physical design, an efficient timing optimization methodology is needed. The conventional timing convergence methodology is inefficient at many points due to its poor design convergence and it performs timing optimization only by re-synthesizing the data path of the design. However, few design cases require the choice of Engineering Change Order (ECO) technique and clock-path timing optimization technique to meet the design convergence. In this research work, an Improved ECO (IECO) framework model is proposed. This proposed framework model suggests both data path and clock path timing optimization techniques with improved ECO patches. Both SOC design and benchmark circuitries are implemented in 14 nm technology node. Synopsys primetime and IC compiler tools have been used for this research work. For the considered SOC design, the conventional flow improves violation path fixing to 96.43%, unified ECO fixes 97.74% of violating path whereas the proposed framework fixed almost 99.07% of violation path within two iterations. The proposed framework model is tested in IWLS 256 tap FIR filter and ISCAS C2670 benchmark circuitries as a result 97.96 and 97.01% of violating path are fixed by proposed method.

Embedded computers are ubiquitous in products across various industries, including the automotive and medical industries, and in consumer goods such as appliances and entertainment devices. These specialized computing systems utilize Systems on Chips (SoCs), devices that are made up of one or more main microprocessor cores. SoCs are augmented with sub-blocks that perform dedicated tasks to support the system. Sub-blocks contain custom logic or small-footprint microprocessors, depending upon their complexity, and perform support functions such as clock generation, device testing, phase-locked loop synchronization and peripheral management for interfaces such as a Universal Serial Bus (USB) or Serial Peripheral Interface (SPI). SoC designers have traditionally obtained sub-blocks from commercial vendors. While these sub-blocks have well-defined interfaces, their internal implementations are opaque. Without visibility of the specifics of the implementation, SoC designers are limited to the degree to which they can optimize these off-the-shelf sub-blocks. The result is that power and area constraints are dictated by the design of a third-party vendor. This work introduces a novel idea: using an open-source, small, multitasking, real-time operating system inside an SoC sub-block to manage multiple processes, thereby conserving code space. This OS is TurbOS, a new operating system whose primary goal is to provide the highest performance using the least amount of space. It is written in the assembly language of a new pipelined 16-bit microprocessor developed at the University of Florida, the Turbo9. TurbOS is derived from and incorporates the design benefits of an existing operating system called NitrOS-9, and reduces the code size from its progenitor by nearly 20%. Furthermore, it is over 80% smaller than the popular FreeRTOS operating system. TurbOS delivers a rich feature set for managing memory and process resources that are useful in SoC sub-block applications in an extremely small footprint of only 3 kilobytes.

Static Random Access Memory (SRAM) is one of the main peripherals in all the Very-large-scale Integrated (VLSI) chips, which enact a vital part in all executable applications. The write ability and read stability are prime factors with low power supply and improve operation speed with temperature, process, and voltage variations. In VLSI design, the System on Chip (SoC) performance is improved by applying low power supply and change in few Pico seconds of cycle times or memory access. The read/write operation is not accurate in lower supply voltage because it will not flip to the desired voltage levels. For improving performance, proposed an SRAM cell to flip to the desired voltage levels to reduce readability failures in low supply voltages. The additional requirement is needed to increase the chip’s performance with lower supply voltages, and continuously additional circuit techniques are needed for obtaining the SRAM memory’s readability and writing ability. In this paper, different performance improvement methods of SRAM memory cells are analyzed. The reduced word line voltage read assist circuit is designed for the SRAM memory cell.

Tissues- and organs-on-chips are microphysiological systems (MPSs) that model the architectural and functional complexity of human tissues and organs that is lacking in conventional cell monolayer cultures. While substantial progress has been made in a variety of tissues and organs, chips recapitulating immune responses have not advanced as rapidly. This review discusses recent progress in MPSs for the investigation of immune responses. To illustrate recent developments, we focus on two cases in point: immunocompetent tumor microenvironment-on-a-chip devices that incorporate stromal and immune cell components and pathomimetic modeling of human mucosal immunity and inflammatory crosstalk. More broadly, we discuss the development of systems immunology-on-a-chip devices that integrate microfluidic engineering approaches with high-throughput omics measurements and emerging immunological applications of MPSs. Human tumor immune microenvironment-on-a-chip models have been developed to emulate cell-type-dependent interactions, physical and chemical perturbations, and the infiltration and cytotoxicity of therapeutic antitumor lymphocytes and clinically relevant immunomodulatory agents.Intestinal inflammation-on-a-chip models recapitulating the 3D intestinal transmural interface have been developed to discover how pathophysiological factors impair the intercellular crosstalk in the epithelium-microbiome-immune axis and trigger chronic inflammatory immune responses.Combining engineered microphysiological immune system responses with high-throughput multiomics measurements at the single-cell level facilitates a systems immunology-on-a-chip approach to gain novel insights into immune disorders.Immune cells are being incorporated in tissues- and organs-on-chips modeling a variety of diseases.

Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.

Translational challenges associated with reductionist modeling approaches, as well as ethical concerns and economic implications of small animal testing, drive the need for developing microphysiological neural systems for modeling human neurological diseases, disorders, and injuries. Here, we provide a comprehensive review of microphysiological brain and neural systems-on-a-chip (NSCs) for modeling higher order trajectories in the human nervous system. Societal, economic, and national security impacts of neurological diseases, disorders, and injuries are highlighted to identify critical NSC application spaces. Hierarchical design and manufacturing of NSCs are discussed with distinction for surface- and bulk-based systems. Three broad NSC classes are identified and reviewed: microfluidic NSCs, compartmentalized NSCs, and hydrogel NSCs. Emerging areas and future directions are highlighted, including the application of 3D printing to design and manufacturing of next-generation NSCs, the use of stem cells for constructing patient-specific NSCs, and the application of human NSCs to 'personalized neurology'. Technical hurdles and remaining challenges are discussed. This review identifies the state-of-the-art design methodologies, manufacturing approaches, and performance capabilities of NSCs. This work suggests NSCs appear poised to revolutionize the modeling of human neurological diseases, disorders, and injuries.

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency.