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This study presents the first implementation of multilayer neural networks on a memristor/complementary metal‐oxide‐semiconductor (CMOS)‐integrated system‐on‐chip (SoC) to simultaneously detect multiple diseases. To overcome limitations in medical data, generative artificial intelligence techniques are used to enhance the dataset, improving the classifier's robustness and diversity. The system achieves notable performance with low latency, high accuracy (91.82%), and energy efficiency, facilitated by end‐to‐end execution on a memristor‐based SoC with ten 256 × 256 crossbar arrays and an integrated on‐chip processor. This research showcases the transformative potential of memristive in‐memory computing hardware in accelerating machine learning applications for medical diagnostics. A robust disease detection system, which is capable of the early prevention of acute myocardial infarction and the detection of liver cancer, is implemented on a memristive system‐on‐chip (SoC). A fully integrated SoC is utilized to ensure the system's portability, low latency, high accuracy, and energy efficiency for medical analysis.

The Network on Chip architecture’s performance metrics and inter-core communication are significantly impacted by the acceleration of the evolution of the components integrated on a single chip. Therefore, it is crucial to offer an effective mapping between the cores so that communication between them improves in order to solve such problems. Throughput and latency both have a higher impact on outperforming the network’s performance in NoC. In this research paper, an efficient mapping strategy implemented on the real-time embedded applications named ERTEAM is presented. In this algorithm, based on the minimum core average distance the mapping region is finalized, ensuring the overall mapping area reduced. The PE’s mapped according to the minimum communication energy in the selected mapping region. This research is evaluated on a set of embedded applications, which reveals a reduction in latency at 12.3% and 8.4%, the simulation time reduces at an average of 19% and 9.6%, the throughput increases at 14.5% and 7.8% and reduces the communication energy by 15.6% and 5.2% against Branch and Bound Based Mapping (BBPCR) and segmented brute-force mapping respectively. The proposed ERTEAM is simulated and tested on Xilinxs Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit using Xilinx Vivado 2020.2 software platform. The obtained hardware implementation results outperformed the delay and area metrics.

With the advancement in technology, it is now possible to integrate hundreds of cores onto single silicon semiconductor chip or silicon die. In order to provide communication between these cores, large number of resources are required and it leads to the communication problem in System-on- Chip (SoC), which is solved by introduction of Networks-on-Chip (NoC). NoC proves to be most efficient in terms of flexibility, scalability and parallelism. In this paper, the proposed mapping algorithms, Horological Mapping (HorMAP), Rotational Mapping (RtMAP) and Divide and Conquer Mapping (DACMAP) for mapping of tasks onto cores, basically concentrate on the optimization of latency, queuing time, service time and energy consumption of topology at constant bandwidth required. The experimental results discussed in this paper shows the comparison of proposed algorithms with traditional random mapping algorithm. In this paper, 2D mesh topology with XY routing is considered for the simulation of proposed algorithms.

This article presents a design method for a miniaturized, Circularly Polarized (CP), concentric ring-shaped monopole on-chip antenna for 24 GHz short-range application. The proposed antenna covers a 22-29 GHz automotive radar spectrum with a resonance at 24 GHz. Taking a simple circular ring-shaped patch as the reference antenna, this study introduces a small gap in the closed-loop structure that helps provide the required travelling wave current distribution to realize the CP property. Then, a smaller circular ring is incorporated inside the reference antenna to improve the antenna performance in terms of the CP characteristics. Finally, the proposed antenna is tuned to obtain the CP characteristics in the desired band ranging from 23.2 GHz to 27 GHz with 3-dB with Axial Ratio (AR) bandwidth of 3.8 GHz. It offers a maximum gain of -4.5 dBi and wide angular range coverage (HPBW > 75° in both E and H-plane). The standard CMOS process with only one level of mask (metal patterning) is used to better understand the functions of the designed antenna. Compact size (3.8 mm x 4 mm x 0.678 mm), simple design layout, and high performance make the antenna a suitable candidate for System-on-Chip (S°C) application.

System on chip (SoC) is a microchip which integrates many semiconductor devices into a single chip. The complete system that is integrated with many components and circuits has to be tested for its performance. At the same time, testing of SoC should not affect the final cost of the chip. The production cost of each and every chip can be reduced by minimizing the test time of each SoC. The testing time of each SoC can be minimized by using test scheduling techniques more efficiently and effectively. In this paper, artificial intelligence-based natural-inspired techniques such as ACO, MACO, ABC, bat and firefly algorithms are proposed to perform effective test scheduling, thereby reducing the total cost of the chip. The proposed algorithms are implemented on d695 and p22810 benchmark circuits for various values of TAM widths. The performance of the various algorithms was evaluated, and it is inferred that among the several algorithms used bat algorithm performs much better in reducing the overall testing time of SoC, and hence, the SoC cost is also reduced.

With the goal of supporting close-range observation tasks of a spherical amphibious robot, such as ecological observations and intelligent surveillance, a moving target detection and tracking system was designed and implemented in this study. Given the restrictions presented by the amphibious environment and the small-sized spherical amphibious robot, an industrial camera and vision algorithms using adaptive appearance models were adopted to construct the proposed system. To handle the problem of light scattering and absorption in the underwater environment, the multi-scale retinex with color restoration algorithm was used for image enhancement. Given the environmental disturbances in practical amphibious scenarios, the Gaussian mixture model was used to detect moving targets entering the field of view of the robot. A fast compressive tracker with a Kalman prediction mechanism was used to track the specified target. Considering the limited load space and the unique mechanical structure of the robot, the proposed vision system was fabricated with a low power system-on-chip using an asymmetric and heterogeneous computing architecture. Experimental results confirmed the validity and high efficiency of the proposed system. The design presented in this paper is able to meet future demands of spherical amphibious robots in biological monitoring and multi-robot cooperation.

The ever-increasing demand for high performance in the time-critical, low-power embedded domain drives the adoption of powerful but unpredictable, heterogeneous Systems-on-Chip. On these platforms, the main source of unpredictability—the shared memory subsystem—has been widely studied, and several approaches to mitigate undesired effects have been proposed over the years. Among them, performance-counter-based regulation methods have proved particularly successful. Unfortunately, such regulation methods require precise knowledge of each task’s memory consumption and cannot be extended to isolate mixed-criticality tasks running on the same core as the regulation budget is shared. Moreover, the desirable combination of these methodologies with well-known time-isolation techniques—such as server-based reservations—is still an uncharted territory and lacks a precise characterization of possible benefits and limitations. Recognizing the importance of such consolidation for designing predictable real-time systems, we introduce MCTI (Mixed-Criticality Task-based Isolation) as a first initial step in this direction. MCTI is a hardware/software co-design architecture that aims to improve both CPU and memory isolations among tasks with different criticalities even when they share the same CPU. In order to ascertain the correct behavior and distill the benefits of MCTI, we implemented and tested the proposed prototype architecture on a widely available off-the-shelf platform. The evaluation of our prototype shows that (1) MCTI helps shield critical tasks from concurrent non-critical tasks sharing the same memory budget, with only a limited increase in response time being observed, and (2) critical tasks running under memory stress exhibit an average response time close to that achieved when running without memory stress.

This work presents Chronos-V , a Many-Core System-on-Chip (MCSoC) that adopts abstract hardware modeling, executing the FreeRTOS Operating System (OS) at each processing element (PE). Chronos-V  is a heterogeneous architecture with two regions: (i) General Purpose Processing Elements (GPPE), responsible for executing user applications; (ii) peripherals that provide IO capabilities or hardware acceleration to the system. Besides the standard goal of high-level models, design space exploration at early design stages with reduced simulation time, our goal is to advance the state-of-the-art in the MCSoC research field by proposing an architecture with hardware and software support for management techniques. As a case study, we present an ODA (Observe-Decide-Actuate) loop for thermal management, comparing it to a dark silicon patterning mapping in a platform with 196 PEs. Thermal maps show the benefits of using dynamic thermal management regarding hotspot avoidance and temperature reduction.

Many current embedded systems comprise heterogeneous computing components including quite powerful GPUs, which enables their application across diverse sectors. This study demonstrates the efficient execution of a medium-sized self-supervised audio spectrogram transformer (SSAST) model on a low-power system-on-chip (SoC). Through comprehensive evaluation, including real time inference scenarios, we show that GPUs outperform multi-core CPUs in inference processes. Optimization techniques such as adjusting batch size, model compilation with TensorRT, and reducing data precision significantly enhance inference time, energy consumption, and memory usage. In particular, negligible accuracy degradation is observed, with post-training quantization to 8-bit integers showing less than 1% loss. This research underscores the feasibility of deploying transformer neural networks on low-power embedded devices, ensuring efficiency in time, energy, and memory, while maintaining the accuracy of the results.

This paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before reviewing SoC design methodologies and tools. The fundamentals of SoC design flows are laid out. The paper then exposes the crucial role of the intellectual property (IP) industry in the relentless improvements in performance, power, area, and cost (PPAC) attributes of SoCs. High abstraction levels in design capture and increasingly automated design tools (e.g., for verification and validation, synthesis, place, and route) continue to push the boundaries. Aerospace and automotive domains are included as brief case studies. This paper also presents current and future trends in SoC design and implementation including the rising, evolution, and usage of machine learning (ML) and artificial intelligence (AI) algorithms, techniques, and tools, which promise even greater PPAC optimizations.