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The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. The hardware Trojans affecting a circuit’s reliability do not tend to alter the circuit layout. These Trojans often manifest as an increased delay in certain parts of the circuit. These delay faults easily escape during the integrated circuits (IC) testing phase, hence are difficult to detect. If additional patterns to detect delay faults are generated during the test pattern generation stage, then reliability attacks can be detected early without any hardware overhead. This paper proposes a novel method to generate patterns that trigger Trojans without altering the circuit model. The generated patterns’ ability to diagnose clustered Trojans are also analyzed. The proposed method uses only single fault simulation to detect clustered Trojans, thereby reducing the computational complexity. Experimental results show that the proposed algorithm has a detection ratio of 99.99% when applied on ISCAS’89, ITC’99 and IWLS’05 benchmark circuits. Experiments on clustered Trojans indicate a 46% and 34% improvement in accuracy and resolution compared to a standard Automatic Test Pattern Generator (ATPG)Tool.

In this paper, an on-chip clock (OCC) controller with bypass function based on an internal phase locked loop (PLL) is designed to test the faults in system on chip (SOC), such as the transition-delay faults and the stuck-at faults. A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by the automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified. The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timing-related defects. Finally, the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

We provide high‐resolution seismic imaging of the central Garlock fault using data recorded by two dense seismic arrays that cross the Ridgecrest rupture zone (B4) and the Garlock fault (A5). Analyses of fault zone head waves and P‐wave delay times at array A5 show that the Garlock fault is a sharp bimaterial interface with P waves traveling ∼5% faster in the northern crustal block. The across‐fault velocity contrast agrees with regional tomography models and generates clear P‐wave reflections in waveforms recorded by array B4. Kirchhoff migration of the reflected waves indicates a near‐vertical fault between 2 and 6 km depth. The P‐wave delay times imply a ∼300‐m‐wide transition zone near the Garlock fault surface trace beneath array A5, offset to the side with faster velocities. The results provide important constraints for derivations of earthquake properties, simulations of ruptures and ground motion, and future imaging studies associated with the Garlock fault. Plain Language Summary Along the northern edge of the Mojave Desert, the Garlock fault intersects the San Andreas fault and is the second largest (∼300 km long) fault in Southern California. It can host M > 7 earthquakes that pose significant seismic hazard to densely populated communities. However, the subsurface structure of the Garlock fault is not well understood due to the sparse seismic network and lack of seismic activity nearby. The 2019 Ridgecrest earthquake sequence in the Eastern California Shear Zone led to a rapid deployment of several dense linear arrays with ∼100 m spacing and apertures of a few kilometers, which cross the Ridgecrest rupture zone and also the Garlock fault. The recorded seismic data is used here to illuminate the internal structure of the central Garlock fault. Analyses of P‐wave delay times and waves refracted along and reflected by the fault interface indicate a near‐vertical Garlock fault that separates two distinctive crustal blocks with different wave speeds. The resolved high‐resolution fault zone image can have important implications for multiple studies associated with the Garlock fault. Key Points We image the central Garlock fault using data of aftershocks of the 2019 Ridgecrest earthquake recorded by two dense linear arrays A P‐wave velocity contrast across the fault (∼5% faster in the north) generates clear fault zone head and reflected waves Kirchhoff migration of P waves reflected by the fault indicates a near‐vertical interface with a sharp impedance contrast

Given fault false alarm and fault control failure caused by the decrease of fault identification accuracy and fault delay of Switched Reluctance Motor (SRM) power converter in complex working conditions, a method based on the Interactive Multi-Model (IMM) algorithm was proposed in this paper. Besides, the corresponding equivalent circuit models were established according to the different working states of the SRM power converter. The Kalman filter was employed to estimate the state of the model, and the fault detection and location were realized depending on the residual signal. Additionally, a transition probability correction function of the IMM was constructed using the difference of the n-th order to suppress the influence of external disturbance on the fault diagnosis accuracy. Concurrently, a model jump threshold was introduced to reduce delay when the matched model was switched, so as to realize the rapid separation of faults and effective fault control. The simulation and experiment results demonstrate that the IMM algorithm based on low delay anti-interference can effectively reduce the influence of complex working conditions, improve the anti-interference ability of SRM power converter fault diagnosis, and identify fault information accurately and quickly.

In this paper, we explore finite-time H ∞ synchronization control for a class of discrete-time interval type-2 fuzzy Markov jump systems (FMJSs) which include partially unknown transition probabilities, randomly occurring coupling delays, and the controller with stochastic failures. A quantized dynamic event-triggered mechanism is suggested by incorporating the hysteresis-uniform quantizer with a dynamic event-triggered scheme to further reduce data communication overhead. Utilizing the mode-dependent Lyapunov function, the finite-time H ∞ synchronization problem of FMJSs is studied in depth from the mean-square sense. Based on the reciprocal convex method and Wirtinger’s integral inequality, sufficient conditions of the FMJSs synchronization are derived. Finally, the single-link robotic arm systems and H e ´ non systems are utilized to illustrate the practicality and validity of the proposed scheme.

A deep understanding of the dynamical behavior in the parameter-state space plays a vital role in both the optimal design and motion control of mechanical systems. By combining the GPU parallel computing technique with two determinate indicators, namely the Lyapunov exponents and Poincaré section, this paper presents a detailed study on the two-parameter dynamics of a mechanical governor system with different time delays. By identifying different responses in the two-parameter plane, the effect of time delay on the complexity of the evolutionary process is fully revealed. The path-following calculation scheme and time domain collocation method are used to explore the detailed bifurcation mechanisms. An interesting phenomenon that the number of intersection points of some periodic responses on the specified Poincaré section differs from the actual period characteristics is found in classifying the dynamic behavior. For example, the commonly exhibited period-one orbit may have two or more intersection points on the Poincaré section rather than one point. The variations of the basins of attraction are also discussed in the plane of initial history conditions to demonstrate the multistability phenomena and chaotic transitions.

In this paper, the fault detection problem is discussed for a class of discrete-time singular networked control systems with randomly occurring delays and network-induced delays. The considered randomly occurring delays include the multiple state delays and the infinite-distributed delay. Both of them are assumed to occur in random ways, which are governed by two independent stochastic variables satisfying the Bernoulli binary distribution. Network-induced delays are modeled as a discrete-time homogeneous Markov chain, and the transition probabilities of the Markov chain are partially known. A stochastic Lyapunov functional is constructed to design a full-order fault detection filter guaranteeing that the fault detection dynamics is stochastically admissible with a prescribed H ∞ performance index. Hence, the fault detection filter design problem is converted into a convex optimization problem in terms of a set of linear matrix inequalities. If these linear matrix inequalities are feasible, the corresponding parameters of the designed fault detection filter are determined. Finally, a numerical example is addressed to demonstrate the effectiveness of the developed method.

Test sets that consist of both broadside and skewed-load tests provide improved delay fault coverage for standard-scan circuits. This study describes a static test compaction procedure for such test sets. The unique feature of the procedure is that it can modify the type of a test (from broadside to skewed-load or from skewed-load to broadside) if this contributes to test compaction. Given a test set W, the basic static test compaction procedure described in this study considers for inclusion in the compacted test set both a broadside and a skewed-load test based on every test w ∈ W. It selects the test type that detects the higher number of faults. An improved procedure considers a broadside and a skewed-load test based on a test w ∈ W only if w detects a minimum number of faults (without changing its type). Experimental results demonstrate that the static test compaction procedure is typically able to reduce the sizes of mixed test sets further than a procedure that does not modify test types. The procedure modifies the types of significant numbers of tests before including them in the compacted test set.

This paper focuses on fault detection filter (FDF) design for continuous-time nonlinear Markovian jump systems (NMJSs) with mode-dependent delay and time-varying transition probabilities (TPs). By using a novel Lyapunov-Krasovskii function and based on convex polyhedron technique, a new FDF, as the residual generator, is constructed to guarantee the mean-square exponential stability and a prescribed level of disturbance attenuation for admissible perturbations of NMJSs. Finally, the numerical simulation is carried out to demonstrate the effectiveness of our method.

By adding a few logic gates and one or two modeling flip-flops to the circuit under test (CUT), we create a detection or diagnostic automatic test pattern generation (ATPG) model of transition delay faults usable by a conventional single stuck-at fault test pattern generator. Given a transition delay fault pair, the diagnostic ATPG model can either find an exclusive test or prove the equivalence of the fault pair. Our work offers advantages over existing work. First, the detection of a transition delay fault or the diagnosis of a fault pair can be modeled in only one instead of two or four time-frames of the CUT. Second, an exclusive test can be generated under either launch off capture (LOC) or launch off shift (LOS) mode for a full-scan sequential circuit. Third, the proposed ATPG models can be expanded into two time frames to facilitate the use of combinational ATPG tools, though with lower modeling complexity than was possible before. As a result, the percentage of distinguished transition delay fault pairs is larger and the proposed automatic exclusive test generation system is more time-efficient.