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Optimization of equipment structure and process conditions is essential to obtain thin films with the required properties, such as film thickness, trapped charge density, leakage current, and memory characteristics, that ensure reliability of the corresponding device. In this study, we fabricated metal–insulator–semiconductor (MIS) structure capacitors using HfO2 thin films separately deposited by remote plasma (RP) atomic layer deposition (ALD) and direct-plasma (DP) ALD and determined the optimal process temperature by measuring the leakage current and breakdown strength as functions of process temperature. Additionally, we analyzed the effects of the plasma application method on the charge trapping properties of HfO2 thin films and properties of the interface between Si and HfO2. Subsequently, we synthesized charge-trapping memory (CTM) devices utilizing the deposited thin films as charge-trapping layers (CTLs) and evaluated their memory properties. The results indicated excellent memory window characteristics of the RP-HfO2 MIS capacitors compared to those of the DP-HfO2 MIS capacitors. Moreover, the memory characteristics of the RP-HfO2 CTM devices were outstanding as compared to those of the DP-HfO2 CTM devices. In conclusion, the methodology proposed herein can be useful for future implementations of multiple levels of charge-storage nonvolatile memories or synaptic devices that require many states.

Silicon-based vertical double-diffused MOSFET (VDMOS) devices are important components of the power system of spacecraft. However, VDMOS is sensitive to the total ionizing dose (TID) effect and may have TID response variability. The within-batch TID response variability on silicon-based VDMOS devices is studied by the 60Co gamma-ray irradiation experiment in this paper. The variations in device parameters after irradiation is obtained, and the damage mechanism is revealed. Experimental results show that the standard deviations of threshold voltage, subthreshold swing, output capacitance, and diode forward voltage increase, while the standard deviation of maximum transconductance decreases after irradiation. The standard deviation of on-state resistance is basically unchanged before and after irradiation. By separating the trapped charges generated by TID irradiation, it is found that the deviation of the oxide trapped charges and the interface traps increase with the increase in the total dose. The reasons for the variation in device parameters after irradiation are revealed by establishing the relationship between the trapped charges and the electrical parameters before and after irradiation.

Polymer electrets are increasingly getting application in a very wide range. However, its charge trapped mechanism is still poorly understood. It is always challenging how to improve its charge trapped ability and to enhance its performance stability. In this study, a charge trapped mechanism, quasi-dipole model, is proposed for semi-crystalline polymer electrets. Every grain of crystallite is viewed as a dipole based on the polarisation effect between crystalline and amorphous region when charged. The energy level of the charge trap has a dependence on the crystallite structure. The more regular the crystallite grain structure the better charge stability is. The melt-blown polypropylene (MBPP) electret fabrics with α or mesomorphic crystallite are used as the model material to verify the rationality of the mechanism. The experiment results from thermally stimulating discharge and X-ray diffraction proved that the charge-trapped stability could be improved by means of transformation from meso-crystalline to α crystalline structure. The MBPP fabric containing α-crystallite shows much better charge trapped performance than one containing mesomorphic-crystallite because of more regular structure in α crystallite. The findings not only present new insight into charge-trapped phenomena in polymer electrets, but also provide innovation for the processing technology of polymer electret materials.

In this paper, the 650 V N-channel GaN MOSFETs are chosen as the research object to study the radiation and annealing effects under 1 MeV electron irradiation. The output, transfer, and breakdown characteristics are measured before and after electron irradiation. The experimental results show the variation of the I-V curves after irradiation, which is related to the increased conductivity due to the generation of an oxide charge in the GaN MOSFETs. However, the gradual formation of the interface trapped charge offsets the effect of the oxide charge, which decreases the conductivity of the GaN MOSFETs and the drain-source current. The long-term annealing at room temperature degrades the interface trapped charges, leading to the restoration of the I-V characteristics. After room temperature annealing, the breakdown voltage is still higher than the unirradiated level, and this is because the displacement defects caused by electron irradiation cannot be recovered at room temperature.

NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction (ΔGm,max) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories.

T his paper examines, an electrostatically configured Nano-Tube Tunnel Field-Effect Transistor (ED-NTTFET). During the fabrication process, different charges such as fixed charge, oxide trapped charge, and interface trapped charge have been produced at the gate oxide interface. So the effect of positive and negative interface trapped charge (+ITC & -ITC) has been proposed for the first time for electrostatic doped-based Nano-Tube TFET (ED-NTTFET). There are two types of techniques, charge plasma (EP) based technique and electrostatic doped (ED) technique is used to produce the induced charge in the intrinsic channel region. In the charged plasma (CP) technique, the metal work-function is used to produce the induced charge while in the electrostatic doped (ED) technique electrostatic voltage is applied across the source and drain side to produce the induced charge in the intrinsic channel region. Analysis of the various device parameters such as hole/electron concentration, energy diagram, electric field, tunneling rate, driving current, OFF current, ON current, I ON /I OFF , threshold voltage, and average sub-threshold slope in the presence of interface trapped charge (ITC). Due to positive interface trapped charge electric field and band to band tunneling rates are improved. So the drain current of the device also improved from the 2.94*10 −5 A/um 2 to 5.35*10 −5 A/um 2 . Linearity parameters such as second & third order trans-conductance (g m2 & g m3 ), second & third order voltage intercept point (VIP2 & VIP3), second & third order harmonics distortions (HD2 & HD3) and intermodulation distortions (IMD) have been discussed. The negative interface trapped charge (-ITC) degrades the linearity parameter of the device and the positive interface trapped charge (+ITC) improves the linearity parameter of the device. The proposed electrostatic doped nano-tube TFET (ED-NTTFET) produced higher cut-off frequency at lowers operating gate voltage.

In this study, the relationship between thermal ageing and charge trapping properties of epoxy-based nanocomposites has been investigated. With ageing, any dielectric material undergoes thorough degradation. This degradation significantly affects the space charge accumulation and charge trapping behaviour of the dielectric, which are very important parameters for insulation health under high-voltage direct current (HVDC) environment. In this work, an improved model based on the isothermal relaxation current (IRC) has been developed to study the charge trapping behaviour of pure epoxy and epoxy alumina (Al2O3) nano-composites at different ageing conditions. A methodology based on polarisation–depolarisation current (PDC) measurements has been proposed to identify the current component due to a dipolar relaxation in measured total IRC. This will help to identify the trap distribution characteristics more accurately compared to conventional IRC measurements. It was experimentally observed that the addition of nanoparticles significantly reduces trapped charge formation and reduces thermal degradation. It is observed that aging leads to the generation of deeper traps, while the addition of Al2O3 nanoparticles mainly enhances the density of shallow traps. Results presented in this work indicate that epoxy–alumina nanocomposites are very much suitable in HVDC applications from the perspective of trapped charge accumulation.

In this work, an innovative architecture of gate underlap junctionless double-gate MOSFET has been introduced with the idea of using triangular oxide layers to control the electric field near the drain side. A two-dimensional analytical model for the device has been developed based on 2D Poisson’s equation. We have applied Schwartz-Christoffel transformation to model the gate capacitance in the overlap region and conformal mapping to model the fringing electric flux in the gate underlap region and derived exclusive expressions for central potential, drain current, threshold voltage and subthreshold slope subsequently. TCAD tools have been adopted to validate our model. The results emphasize the effects of various device dimensions, especially the maximum oxide thickness and underlap length on various device parameters. The model is able to predict the impact of trapped charges on various device parameters. The structure exhibits excellent control over short channel effects and good designing flexibility obtained by varying the oxide geometry. We have also presented an application of the structure in the form of a CMOS inverter that yields promising results for low-power applications.

The present endeavor attempts to develop an explicit threshold voltage model of linearly graded work function engineered Silicon-On-Insulator MOSFET considering the effects of localized charges trapped at front high-k gate stack/channel and buried oxide layer/channel interfaces. As the accumulation of such equivalent oxide charges modulate the flat band voltage and alter the threshold voltage characteristics of the device, the inclusion of such effects is inexorable while formulating its analytical model. Hence, analytical methodology based extensive study of the potential distribution and threshold voltage behavior of the device affected by positive/negative trapped charges is demonstrated here by varying the channel thickness, high-k dielectrics and drain bias with subsequent comparison with a fresh SOI MOSFET equivalent. All analytical corollaries are compared with relevant ATLAS simulated data to corroborate the eminence of the derived model.

This paper proposed a step-varied 6.5 kV SiC field limiting ring (FLR) termination structure, which features six distinct ring structural characteristics. Especially, the ring width decreases as the distance from the active region increases, while the loop spacing exhibits the opposite trend. The junction depth was initially investigated for the proposed and conventional structures without a field plate to ensure the breakdown voltage is higher than 8150 V. Then, the field plate is combined to further improve the blocking characteristics. The proposed structure performs a much lower maximum electric field strength and uniform distribution compared to the conventional one. Finally, the oxide trapped charge effects are introduced, while the proposed structure exhibits a weaker reduction in breakdown voltage, indicating it is suitable for high-voltage applications and long-term reliability.