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A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions.

Converter valve is the core component of HVDC system, and its safety operation is significant for the system. However, the ability of thyristor in converter valve to withstand overvoltage is weak. Even transient overvoltage can lead to thyristor breakdown. Thus, thyristor is needed to configure overvoltage protection. The paper analyzes two kinds of thyristor overvoltage protection scheme BTC (Backup Trigger Circuit) and BOD (Break Over Diode), and then sets up PSPICE models to conduct simulation analysis. Finally, the performance of the two kinds of overvoltage protection is verified by practical circuit experiment. The result shows that both protection schemes can satisfy the requirement of thyristor overvoltage protection.

The trigger circuits of high-power thyristors in pulsed power supply (PPS) contain a large number of pulse transformers, switching MOSFETs (SMFETs) and other passive devices. Fast on-off of SMFETs and pulse transformers often lead to differential mode conducted interference (DMCI) problems in trigger circuits of high-power thyristors. This paper mainly disscusses DMCI problems in trigger circuits of high-power thyristors in the following aspects: initially, circuit models of high-frequency parasitic parameters of pulse transformer and SMFET are established; next, principles of DMCI in trigger circuits of high-power thyristors are investigated; furthermore, DMCI suppression methods are also analyzed; ultimately, experiments have been carried out to verify the theoretical analysis.

Internet of things (IoT) based systems require power-efficient circuits to raise the battery lifeline. This study presents a single-ended 8T SRAM cell. The core of the proposed 8T SRAM cell is composed of a Schmitt-Trigger circuit which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. Read operation of the proposed cell is conducted using the shared footer per word transistor. The write path is cut-off during the read operation, improving RSNM. A transmission gate placed in the cell core is used to cut the feedback path during write operation. To prove superiority of the proposed cell it is compared with four state-of-the-art SRAM cells under identical conditions on Cadence Virtuoso using 45nm technology at VDD=0.8 V. The proposed circuit shows a 135.74 % improvement in terms of RSNM and a 44.04 % improvement in terms of peak-to-peak power compared to the 6T DTMOS Cell.

In this paper, for the strong electromagnetic interference environment, a kind of 6500V/1000A thyristor controller is designed. The controller includes a main trigger state detection module, an optical fiber communication module, a temperature detection module, a main controller module, and a trigger module. It highlights the thyristor trigger circuit and its corresponding detection circuit, this trigger circuit can provide a strong trigger pulse to ensure a reliable triggering of thyristors at any moment, the detection circuit can improve the reliability of the system.

This paper focuses on the differential-mode (DM) noise of high-power thyristor (HPT) trigger circuit with switching-mode power supply (SMPS) in capacitive pulsed power supply (CPPS). Parasitic parameter models of components are discussed and analyzed. Based on the parasitic parameter models of components, a DM noise prediction model of HPT trigger circuit with SMPS is developed. The generation mechanism and propagation paths of the DM noise in HPT trigger circuit with SMPS are investigated. To reduce the DM noise, a capacitive SMPS technique is adopted in the HPT trigger circuit with SMPS. Simulation results validate the theoretical analysis.

Purpose As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time. Design/methodology/approach Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness. Findings The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+. Originality/value Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.

The requirement of high speed low power square wave generators that yield spike free signal enabled the design of Schmitt trigger circuit. The designs BJT or FET based circuits have disadvantages like spikes in output signal cannot be suppressed, the output signal gain control is required, low packing density, considerable power dissipation, etc. This has paved way to development of CMOS based design. Further low power requirement enabled the CMOS based low power design aspects for the Schmitt trigger circuit. The designs are modeled in DSCH and Microwind tools for schematic and layout development at various technologies like 90, 65, 45, 32 and 22 nm. The choice of designs used are basic Schmitt trigger circuit, dynamic CMOS logic based Schmitt trigger circuit, pseudo NMOS based Schmitt trigger circuit, weak PMOS domino based Schmitt trigger circuit, NORA logic based Schmitt trigger circuit, leakage control transistor (LECTOR) based Schmitt trigger circuit, GALEOR (gated leakage transistor) based Schmitt trigger circuit and feed-forward leakage self-suppression logic (FFLSSL) based Schmitt trigger circuit. While the least number of transistors used are in the pseudo NMOS based Schmitt trigger circuit and highest number of transistors are used in NORA logic based Schmitt trigger circuit. Still pseudo NMOS requires ratioed logic which is a measure drawback. The pseudo NMOS logic based Schmitt trigger circuit occupies very less area by at least 27.027%. The power dissipation is very less in FFLSSL based Schmitt Trigger circuit by at least 75%. The delay is less in FFLSSL based Schmitt trigger circuit by at least 10.15%.

This study has clarified the optoelectronic devices based on configurable hysteresis of Schmitt trigger circuit control with the employment of CMOS technology. Schmitt trigger (ST) is an electronics circuit, widely used in a sensor network to detect a signal with low amplitude in a noisy environment. It converts a variable input signal to a constant output level. In contrast to the comparator, an ST offers two independent switching voltages with positive feedback that enhances the depth of the switching threshold. Hysteresis width is an inbuilt feature of the trigger circuit, removing the irregularities or noise near the threshold region and shaping it into smooth output. The hysteresis width can be adjusted by a suitable variation in the aspect ratio of input and feedback transistors. In this work, conventional ST architecture modifies by configuring the series and/or parallel connection of n-channel and p-channel MOS devices to adjust the hysteresis voltage. The simulation result is obtained with Cadence Spectra with BSIM3V3 device models at 90 nm CMOS technology, and hysteresis width falls by reducing the feedback ratio of the increase with feedback ratio.

A power clamp circuit, which has good immunity to false trigger under fast power-on conditions with a 20 ns rising edge, is proposed in this paper. The proposed circuit has a separate detection component and an on-time control component which enable it to distinguish between electrostatic discharge (ESD) events and fast power-on events. As opposed to other on-time control techniques, instead of large resistors or capacitors, which can cause a large occupation of the layout area, we use a capacitive voltage-biased p-channel MOSFET in the on-time control part of the proposed circuit. The capacitive voltage-biased p-channel MOSFET is in the saturation region after the ESD event is detected, which can serve as a large equivalent resistance (~106 Ω) in the structure. The proposed power clamp circuit offers several advantages compared to the traditional circuit, such as having at least 70% area savings in the trigger circuit area (30% area savings in the whole circuit area), supporting a power supply ramp time as fast as 20 ns, dissipating the ESD energy more cleanly with little residual charge, and recovering faster from false triggers. The rail clamp circuit also offers robust performance in an industry-standard PVT (process, voltage, and temperature) space and has been verified by the simulation results. Showing good performance of human body model (HBM) endurance and high immunity to false trigger, the proposed power clamp circuit has great potential for application in ESD protection.