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3,275 result(s) for "Tunnel junctions"
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Integer factorization using stochastic magnetic tunnel junctions
Conventional computers operate deterministically using strings of zeros and ones called bits to represent information in binary code. Despite the evolution of conventional computers into sophisticated machines, there are many classes of problems that they cannot efficiently address, including inference, invertible logic, sampling and optimization, leading to considerable interest in alternative computing schemes. Quantum computing, which uses qubits to represent a superposition of 0 and 1, is expected to perform these tasks efficiently 1 – 3 . However, decoherence and the current requirement for cryogenic operation 4 , as well as the limited many-body interactions that can be implemented, pose considerable challenges. Probabilistic computing 1 , 5 – 7 is another unconventional computation scheme that shares similar concepts with quantum computing but is not limited by the above challenges. The key role is played by a probabilistic bit (a p-bit)—a robust, classical entity fluctuating in time between 0 and 1, which interacts with other p-bits in the same system using principles inspired by neural networks 8 . Here we present a proof-of-concept experiment for probabilistic computing using spintronics technology, and demonstrate integer factorization, an illustrative example of the optimization class of problems addressed by adiabatic 9 and gated 2 quantum computing. Nanoscale magnetic tunnel junctions showing stochastic behaviour are developed by modifying market-ready magnetoresistive random-access memory technology 10 , 11 and are used to implement three-terminal p-bits that operate at room temperature. The p-bits are electrically connected to form a functional asynchronous network, to which a modified adiabatic quantum computing algorithm that implements three- and four-body interactions is applied. Factorization of integers up to 945 is demonstrated with this rudimentary asynchronous probabilistic computer using eight correlated p-bits, and the results show good agreement with theoretical predictions, thus providing a potentially scalable hardware approach to the difficult problems of optimization and sampling. A probabilistic computer utilizing probabilistic bits, or p-bits, is implemented with stochastic nanomagnetic devices in a neural-network-inspired electrical circuit operating at room temperature and demonstrates integer factorization up to 945.
Multi-ferroic and magnetoelectric materials and interfaces
The existence of multiple ferroic orders in the same material and the coupling between them have been known for decades. However, these phenomena have mostly remained the theoretical domain owing to the fact that in single-phase materials such couplings are rare and weak. This situation has changed dramatically recently for at least two reasons: first, advances in materials fabrication have made it possible to manufacture these materials in structures of lower dimensionality, such as thin films or wires, or in compound structures such as laminates and epitaxial-layered heterostructures. In these designed materials, new degrees of freedom are accessible in which the coupling between ferroic orders can be greatly enhanced. Second, the miniaturization trend in conventional electronics is approaching the limits beyond which the reduction of the electronic element is becoming more and more difficult. One way to continue the current trends in computer power and storage increase, without further size reduction, is to use multi-functional materials that would enable new device capabilities. Here, we review the field of multi-ferroic (MF) and magnetoelectric (ME) materials, putting the emphasis on electronic effects at ME interfaces and MF tunnel junctions.
Spintronic devices: a promising alternative to CMOS devices
The field of spintronics has attracted tremendous attention recently owing to its ability to offer a solution for the present-day problem of increased power dissipation in electronic circuits while scaling down the technology. Spintronic-based structures utilize electron’s spin degree of freedom, which makes it unique with zero standby leakage, low power consumption, infinite endurance, a good read and write performance, nonvolatile nature, and easy 3D integration capability with the present-day electronic circuits based on CMOS technology. All these advantages have catapulted the aggressive research activities to employ spintronic devices in memory units and also revamped the concept of processing-in-memory architecture for the future. This review article explores the essential milestones in the evolutionary field of spintronics. It includes various physical phenomena such as the giant magnetoresistance effect, tunnel magnetoresistance effect, spin-transfer torque, spin Hall effect, voltage-controlled magnetic anisotropy effect, and current-induced domain wall/skyrmions motion. Further, various spintronic devices such as spin valves, magnetic tunnel junctions, domain wall-based race track memory, all spin logic devices, and recently buzzing skyrmions and hybrid magnetic/silicon-based devices are discussed. A detailed description of various switching mechanisms to write the information in these spintronic devices is also reviewed. An overview of hybrid magnetic /silicon-based devices that have the capability to be used for processing-in-memory (logic-in-memory) architecture in the immediate future is described in the end. In this article, we have attempted to introduce a brief history, current status, and future prospectus of the spintronics field for a novice.
Tunable multiple non-volatile resistance states in multiferroic tunnel junctions based on sliding ferroelectric PtTe2
Multiferroic tunnel junctions (MFTJs) own significant potential application in non-volatile memory devices due to their multifunctional characteristics, which has attracted widespread attention. The recent advancements in van der Waals (vdW) multiferroic materials have successfully combined ferromagnetism and ferroelectricity, providing an ideal platform for studying MFTJs at the atomic scale. In this study, we theoretically investigate the spin-dependent transport properties of vdW MFTJs based on sliding ferroelectric barrier layers of PtTe2 using first principles based on density functional theory. Our research shows that multiple non-volatile resistance states can be achieved by controlling the polarization direction of the ferroelectric barrier in Fe3GaTe2/PtTe2/Fe3GeTe2 vdW MFTJs and the magnetization direction of the ferromagnetic electrodes. Specifically, as the ferroelectric material undergoes slippage, the polarization of the ferroelectric barrier shifts from left-oriented (P←) to right-oriented (P→), which induces the tunneling magnetoresistance ratio at the Fermi level increasing from 2.7×107% to 5.7×107%. As the magnetization direction of the ferromagnetic electrodes changes from parallel (M↑↑) to antiparallel (M↑↓), the tunneling electroresistance ratio significantly rises from 9.52% to 155%. Moreover, a nearly 100% spin-filtering efficiency is observed in the four states of MFTJs and the resistance area (RA) product is very small, with the minimum RA product at the Fermi level 0.033 Ω⋅μm2. This research highlights the potential use of the sliding ferroelectricity in bilayer PtTe2 in constructing multistate non-volatile memory and spin filter, and can be used for the development of multifunctional electronic devices.
Crossbar operation of BiFeO3/Ce–CaMnO3 ferroelectric tunnel junctions: From materials to integration
Ferroelectric Tunnel Junctions (FTJs) are a candidate for the hardware realization of synapses in artificial neural networks. The fabrication process for a 784 × 100 crossbar array of 500 nm large FTJs, exhibiting effective On/Off currents ratio in the range 50–100, is presented. First, the epitaxial 4 nm-BiFeO 3 /Ca 0.96 Ce 0.04 MnO 3 //YAlO 3 is combined with Ni electrodes. The oxidation of Ni during the processing affects the polarity of the FTJ and the On/Off ratio, which becomes comparable to that of CMOS-compatible HfZrO 4 junctions. The latter have a wider coercive field distribution: consequently, in test crossbar arrays, BiFeO 3 exhibits a smaller cross-talk than HfZrO 4 . Furthermore, the relatively larger threshold for ferroelectric switching in BiFeO 3 allows the use application of half-programming schemes for supervised and unsupervised learning. Second, the heterostructure is combined with W and Pt electrodes. The design is optimized for the controlled collapse chip connection to neuromorphic circuits. Graphical abstract
The Data Acquisition System for Phase-III of the BeEST Experiment
The BeEST experiment is a precision laboratory search for physics beyond the standard model that measures the electron capture decay of 7 Be implanted into superconducting tunnel junction (STJ) detectors. For Phase-III of the experiment, we constructed a continuously sampling data acquisition system to extract pulse shape and timing information from 16 STJ pixels offline. Four additional pixels are read out with a fast list-mode digitizer, and one with a nuclear MCA already used in the earlier limit-setting phases of the experiment. We present the performance of the data acquisition system and discuss the relative advantages of the different digitizers.
E-Spin: A Stochastic Ising Spin Based on Electrically-Controlled MTJ for Constructing Large-Scale Ising Annealing Systems
With its unique computer paradigm, the Ising annealing machine has become an emerging research direction. The Ising annealing system is highly effective at addressing combinatorial optimization (CO) problems that are difficult for conventional computers to tackle. However, Ising spins, which comprise the Ising system, are difficult to implement in high-performance physical circuits. We propose a novel type of Ising spin based on an electrically-controlled magnetic tunnel junction (MTJ). Electrical operation imparts true randomness, great stability, precise control, compact size, and easy integration to the MTJ-based spin. In addition, simulations demonstrate that the frequency of electrically-controlled stochastic Ising spin (E-spin) is 50 times that of the thermal disturbance MTJ-based spin (p-bit). To develop a large-scale Ising annealing system, up to 64 E-spins are implemented. Our Ising annealing system demonstrates factorization of integers up to 264 with a temporal complexity of around O(n). The proposed E-spin shows superiority in constructing large-scale Ising annealing systems and solving CO problems.
Unconventional computing based on magnetic tunnel junction
The conventional computing method based on the von Neumann architecture is limited by a series of problems such as high energy consumption, finite data exchange bandwidth between processors and storage media, etc., and it is difficult to achieve higher computing efficiency. A more efficient unconventional computing architecture is urgently needed to overcome these problems. Neuromorphic computing and stochastic computing have been considered to be two competitive candidates for unconventional computing, due to their extraordinary potential for energy-efficient and high-performance computing. Although conventional electronic devices can mimic the topology of the human brain, these require high power consumption and large area. Spintronic devices represented by magnetic tunnel junctions (MTJs) exhibit remarkable high-energy efficiency, non-volatility, and similarity to biological nervous systems, making them one of the promising candidates for unconventional computing. In this work, we review the fundamentals of MTJs as well as the development of MTJ-based neurons, synapses, and probabilistic-bit. In the section on neuromorphic computing, we review a variety of neural networks composed of MTJ-based neurons and synapses, including multilayer perceptrons, convolutional neural networks, recurrent neural networks, and spiking neural networks, which are the closest to the biological neural system. In the section on stochastic computing, we review the applications of MTJ-based p-bits, including Boltzmann machines, Ising machines, and Bayesian networks. Furthermore, the challenges to developing these novel technologies are briefly discussed at the end of each section.
Micromagnetic realization of energy-based models using stochastic magnetic tunnel junctions
Energy-based models (EBMs) can bridge physics, machine learning, and statistics. EBMs provide a unified and powerful platform to describe, learn, and optimize complex systems. In this paper, we propose a neuromorphic implementation of EBMs using a network of stochastic magnetic tunnel junctions (MTJs) that can perform energy minimization and solve optimization problems. Our implementation builds on the Object Oriented MicroMagnetic Framework (OOMMF). We derive the different energy terms and map them to the micromagnetic Landau-Lifshitz-Gilbert (LLG) equation. We then develop a C +  + module for EBMs which integrates seamlessly with OOMMF. We demonstrate our implementation on a full set of logic gates using stochastic MTJs networks. Our method offers several advantages, including fast modeling of EBMs with spintronic devices and design insights for stochastic MTJ-based neuromorphic circuits.
Design of a 2–4 Decoder Based on All-Spin Logic and Magnetic Tunnel Junction
A 2–4 decoder based on all-spin logic (ASL) and magnetic tunnel junction (MTJ) is proposed. The decoder employs five-input minority gates to realize three-input NOR gates, which reduces the circuit size compared to the three-input minority gates. Simultaneously, the inputs of the original and reverse variables are implemented by initializing the MTJ fixed layer magnetization in different directions, which avoids the use of inverters. In addition, the 2–4 decoder adopts a single-input single-fan-out (SISF) structure, which reduces the channel length. To illustrate the advantages of the five-input minority gate, inverter-free structure, and SISF structures in designing the proposed 2–4 decoder, a second 2–4 decoder is proposed that uses three-input minority gates, inverters, and a single-input multiple-fan-out structure. Compared with the second decoder, the first decoder has the layout area reduced to 37.9%, the total channel length reduced to 40.8%, and the number of clock cycles reduced to one-third. Importantly, the design methods used in this work, such as multi-input minority gates, SISF structure, and inverter-free structure, provide an interesting approach for designing large-scale ASL logic circuits.