Explore the vast range of titles available.

This book is a comprehensive guide to new design for testability (DFT) methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Key features include up-to-date coverage of design for testability, coverage of industry practices commonly found in commercial DFT tools but not discussed in other books, and numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Practitioners/Researchers in VLSI design and testing; design or test engineers, as well as research institutes will benefit from this book. This book is also appropriate for undergraduate and graduate-level courses in electronic testing, digital systems testing, digital logic test and simulation, and VLSI design.

An expert guide to the new and emerging field of broadband circuits for optical fiber communication This exciting publication makes it easy for readers to enter into and deepen their knowledge of the new and emerging field of broadband circuits for optical fiber communication. The author's selection and organization of material have been developed, tested, and refined from his many industry courses and seminars. Five types of broadband circuits are discussed in detail: * Transimpedance amplifiers * Limiting amplifiers * Automatic gain control (AGC) amplifiers * Lasers drivers * Modulator drivers Essential background on optical fiber, photodetectors, lasers, modulators, and receiver theory is presented to help readers understand the system environment in which these broadband circuits operate. For each circuit type, the main specifications and their impact on system performance are explained and illustrated with numerical values. Next, the circuit concepts are discussed and illustrated with practical implementations. A broad range of circuits in MESFET, HFET, BJT, HBT, BiCMOS, and CMOS technologies is covered. Emphasis is on circuits for digital, continuous-mode transmission in the 2.5 to 40 Gb/s range, typically used in SONET, SDH, and Gigabit Ethernet applications. Burst-mode circuits for passive optical networks (PON) and analog circuits for hybrid fiber-coax (HFC) cable-TV applications also are discussed. Learning aids are provided throughout the text to help readers grasp and apply difficult concepts and techniques, including: * Chapter summaries that highlight the key points * Problem-and-answer sections to help readers apply their new knowledge * Research directions that point to exciting new technological breakthroughs on the horizon * Product examples that show the performance of actual broadband circuits * Appendices that cover eye diagrams, differential circuits, S parameters, transistors, and technologies * A bibliography that leads readers to more complete and in-depth treatment of specialized topics This is a superior learning tool for upper-level undergraduates and graduate-level students in circuit design and optical fiber communication. Unlike other texts that concentrate on analog circuits in general or mostly on optics, this text provides balanced coverage of electronic, optic, and system issues. Professionals in the fiber optic industry will find it an excellent reference, incorporating the latest technology and discoveries in the industry.

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI testing and design-for-testability (DFT) techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly system-on-chip test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

A reprint of the classic text, this book popularized compact modeling of electronic and semiconductor devices and components for college and graduate-school classrooms, and manufacturing engineering, over a decade ago. The first comprehensive book on MOS transistor compact modeling, it was the most cited among similar books in the area and remains the most frequently cited today. The coverage is device-physics based and continues to be relevant to the latest advances in MOS transistor modeling. This is also the only book that discusses in detail how to measure device model parameters required for circuit simulations.

This text covers all the basics of VLSI fabrication and low-level system design. Comprehensive and well-written, it is suitable for courses in VLSI system design and digital integrated circuit analysis and design. Taking a bottom-up approach, the book starts with an overview of logic design principles, before tackling design issues and fabrication. The book includes numerous worked examples and homework problems. It also offers two sets of PowerPoint slides and an instructor's manual upon qualified course adoption.

In this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the “Degradation Delay Model”, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.

Carbon nanotube field-effect transistors (CNTFETs) are increasingly recognized as a viable option for creating high-performance, low-power, and densely integrated circuits (ICs). Advancements in carbon-based electronics, encompassing materials and device technology, have enabled the fabrication of circuits with over 1000 gates, marking carbon-based integrated circuit design as a burgeoning field of research. A critical challenge in the realm of carbon-based very-large-scale integration (VLSI) is the lack of suitable automated design methodologies and infrastructure platforms. In this study, we present the development of a wafer-scale 3 µm carbon-based complementary metal-oxide-semiconductor (CMOS) process design kit (PDK) (3 µm-CNTFETs-PDK) compatible with silicon-based Electronic Design Automation (EDA) tools and VLSI circuit design flow. The proposed 3 µm-CNTFETs-PDK features a contacted gate pitch (CGP) of 21 µm, a gate density of 128 gates/mm 2 , and a transistor density of 554 transistors/mm 2 , with an intrinsic gate delay around 134 ns. Validation of the 3 µm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits. Leveraging the carbon-based PDK and a silicon-based design platform, we successfully implemented a complete 64-bit static random-access memory (SRAM) circuit system for the first time, which exhibited timing, power, and area characteristics of clock@10 kHz, 122.1 µW, 3795 µm × 2810 µm. This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow, thereby laying the groundwork for future carbon-based VLSI advancements.

When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of IC design will be extremely beneficial in this situation, as will be demonstrated further below. If the importance of placement and routing congestion concerns is underappreciated, the IC implementation may experience significant nonlinear problems throughout the process as a result of the underappreciation of placement and routing congestion concerns. The use of standard optimization techniques in integrated circuit design is not the most effective strategy when it comes to precisely estimating nonlinear aspects in the design of integrated circuits. To this end, advanced tools such as Xilinx VIVADO and the ICC2 have been developed, in addition to the ICC1 and VIRTUOSO, to explore for computations and recover the actual parameters that are required to design optimal placement and routing for well-organized and ordered physical design. Furthermore, this work employs the perimeter degree technique (PDT) to measure routing congestion in both horizontal and vertical directions for a silicon chip region and then applies the technique to lower the density of superfluous routing (DSR) (PDT). Recently, a metaheuristic approach to computation has increased in favor, particularly in the last two decades. It is a classic graph theory problem, and it is also a common topic in the field of optimization. However, it does not provide correct information about where and how nodes should be put, despite its popularity. Consequently, in conjunction with the optimized floorplan data, the optimized model created by the Improved Harmonic Search Optimization algorithm undergoes testing and investigation in order to estimate the amount of congestion that occurs during the routing process in VLSI circuit design and to minimize the amount of congestion that occurs.

Multiplication is one of the essential functions in all digital systems. The evaluation of digital system, have brought out new challenges in VLSI (Very Large Scale Integration) designing. Multipliers are generally utilized in digital signal processing. Increasing technology has maximized the demand for rapid and efficient real-time digital signal processing applications. A huge number of multiplier designs have been developed for improving its speed. This manuscript provides an exploration of the different studies that have been conducted since 2015. This manuscript reviews investigation depends on various types of multipliers. A thorough statistical analysis is provided in this review which was conducted by extracting information from 100 papers published between the years 2015–2020. When comparing the adders, obtain the Ripple Carry Adder had lesser area while it had lower speed, in contrast to Carry Select Adders they are great speed but greater area. A Carry Look Ahead Adder sits among spectrum has a suitable balance among complexities of time and area. After designing and comparing the adders, turned to multipliers. At first opted for Parallel Multiplier and then Wallace Tree Multiplier. Meanwhile, learned the amount of delay was greatly decreased while Carry Save Adders were utilized on Wallace Tree applications. In this review, present the comparison and analysis of investigation manuscript depends on several criteria. In general, this manuscript summarizes the current state of knowledge of these multipliers. In this, the comparative analysis depends on timeline, reputation of simulation tools and types of device components are analyzed.