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Hot plasma is highly conductive in the direction parallel to a magnetic field. This often means that the electrical potential will be nearly constant along any given field line. When this is the case, the cross-field voltage drops in open-field-line magnetic confinement devices are limited by the tolerances of the solid materials wherever the field lines impinge on the plasma-facing components. To circumvent this voltage limitation, it is proposed to arrange large voltage drops in the interior of a device, but coexist with much smaller drops on the boundaries. To avoid prohibitively large dissipation requires both preventing substantial drift-flow shear within flux surfaces and preventing large parallel electric fields from driving large parallel currents. It is demonstrated here that both requirements can be met simultaneously, which opens up the possibility for magnetized plasma tolerating steady-state voltage drops far larger than what might be tolerated in material media. In open-field-line magnetic plasma traps, the attainable cross-field voltage drops are limited by the tolerances of the solid materials of the vacuum vessel. Here, the authors demonstrate the possibility of equilibria that isolate large voltage drops to the interior of the plasma, circumventing this limit.

The splitting of quasi-Fermi levels (QFLs) represents a key concept utilized to describe finite-bias operations of semiconductor devices, but its atomic-scale characterization remains a significant challenge. Herein, the nonequilibrium QFL or electrochemical potential profiles within single-molecule junctions obtained from the first-principles multispace constrained-search density-functional formalism are presented. Benchmarking the standard nonequilibrium Green’s function calculation results, it is first established that algorithmically the notion of separate electrode-originated nonlocal QFLs should be maintained within the channel region during self-consistent finite-bias electronic structure calculations. For the insulating hexandithiolate junction, the QFL profiles exhibit discontinuities at the left and right electrode interfaces and across the molecule the accompanying electrostatic potential drops linearly and Landauer residual-resistivity dipoles are uniformly distributed. For the conducting hexatrienedithiolate junction, on the other hand, the electrode QFLs penetrate into the channel region and produce split QFLs. With the highest occupied molecular orbital entering the bias window and becoming a good transport channel, the split QFLs are accompanied by the nonlinear electrostatic potential drop and asymmetric Landauer residual-resistivity dipole formation. Our findings underscore the importance of the first-principles extraction of QFLs in nanoscale junctions and point to a future direction for the computational design of nextgeneration semiconductor devices.

The existing active-type voltage arc suppression methods do not consider the influence of line voltage drop, which leads to the existence of large fault residual current at the fault point for low-resistance grounding fault occurring in the distribution network and affects the reliable extinguishing of the fault arc. In this paper, an active inverter is used to inject a compensating current to the neutral point of the system before and after the fault, and the distance between the fault point and the bus is calculated, then the reference value of the neutral point voltage which controls the fault point voltage to zero can be obtained. A double closed-loop control strategy of current inner loop and voltage outer loop is used to track the voltage reference value. The simulation results show that the proposed method is independent of the exact zero-sequence admittance value, and not only has a good arc suppression effect under different fault conditions, but also can effectively suppress the harmonic components of the fault current.

Interleaving techniques in DC-DC converters enhance the operational redundancy and reduce the current ripple. However, the phase-shifted operation of the interleaved branches results in different mathematical models for high and low values of duty ratio. In applications such as renewable energy integration where wide variations in duty ratios are bound to occur due to the dynamic nature of the source, a single mathematical model cannot represent the interleaved converter for the entire duty ratio range. This is due to the fact that when the duty ratio increases beyond a threshold the conduction period of the interleaved phases overlap, resulting in a different set of operating modes of the converter. Existing literature has not investigated this effect while formulating the mathematical model as it becomes evident only when the parasitic circuit elements are accounted for in the model. Firstly, this paper presents an extensive small-signal of a two-phase interleaved boost converter considering all the internal voltage drops due to parasitic circuit elements. Secondly, this work investigates the variations in the mathematical model due to the presence of parasitic circuit elements, when the interleaved converter operates in phase-shifted mode over a wide range of duty ratio. The proposed model is tested by simulation in MATLAB/Simulink® and validated with a 300W hardware prototype.

Social considerations for a sustainable future lead to market demands for electromobility. Hence, electrical power distribution operators are concerned about the real ongoing problem of the electrification of the transport sector. In this regard, the paper aims to investigate the large-scale integration of electric vehicles in a Swedish distribution network. To this end, the integration pattern is taken into consideration as appears in the literature for other countries and applies to the Swedish culture. Moreover, different charging power levels including smart charging techniques are examined for several percentages of electric vehicles penetration. Industrial simulation tools proven for their accuracy are used for the study. The results indicate that the grid can manage about 50% electric vehicles penetration at its current capacity. This percentage decreases when higher charging power levels apply, while the transformers appear overloaded in many cases. The investigation of alternatives to increase the grid’s capabilities reveal that smart techniques are comparable to the conventional re-dimension of the grid. At present, the increased integration of electric vehicles is manageable by implementing a combination of smart gird and upgrade investments in comparison to technically expensive alternatives based on grid digitalization and algorithms that need to be further confirmed for their reliability for power sharing and energy management.

Bidirectional power switches are used in matrix-or cyclo-converters and in multistage inverter circuits to facilitate high-frequency AC-to-AC conversion. A new 1.2 kV bidirectional MOSFET (BiDFET) with low on-resistance is achieved and demonstrated using two discrete SiC power MOSFET bare die chips, packaged within a four-terminal custom-designed module. Static and dynamic characterization has been carried out to inspect the on-state and switching behaviour of the BiDFET. The BiDFET is shown to have a low forward voltage drop of 0.6 V at a current of 10 A, which is more than 2.5x smaller than previous Si IGBT and SiC MOSFET based bidirectional switch implementations.

Dynamic voltage drop analysis is a critical aspect of chip design in advanced process nodes, where shrinking dimensions, increasing transistor densities, lower operating voltages, and higher frequencies exacerbate power delivery challenges. These challenges, including voltage fluctuations and localized hotspots, directly impact circuit performance and reliability. This article presents a comprehensive dynamic voltage drop analysis using a RISC-V core as a case study. The analysis evaluates the design's susceptibility under variable statistical workload toggle rates, validated with a compute-intensive real workload. A sensitivity analysis examines the impact of package inductance, variable toggle rates, and the role of decoupling capacitors. Additionally, the article investigates the timing implications of voltage drop, demonstrating how voltage fluctuations can result in severe timing violations. The study includes simulations across extended process-voltage-temperature (PVT) corners to examine how process, voltage, and temperature variations influence dynamic voltage drop and circuit reliability. This characterization provides a clear understanding of voltage stability in RISC-V cores under realistic design and operating conditions. Simulations conducted on a 16 nm FinFET process node offer valuable insights into the interplay between dynamic voltage drop, PVT variations, and timing reliability. To the best of our knowledge, this is the first study to perform such an in-depth analysis on a RISC-V core under these conditions.

With the development of intelligent energy metering equipment, traditional signal processing methods have encountered limitations in measuring instantaneous frequency. This article proposes a fast fault location method for electric energy metering equipment based on the Hilbert Huang transform. Initially, the differential voltage drop is measured. Subsequently, variational mode decomposition filtering is applied. Following this, the Hilbert Huang transform is used to calculate the instantaneous frequency and generate a time-frequency diagram. Based on the time-frequency diagram, the fault time is identified at the point of sudden change, and the fault point is determined by integrating this information with the wave velocity. Experimental results demonstrate that this method is applicable to both single and multiple disturbances. It is capable of measuring a -300 V voltage drop and accurately determining the instantaneous frequency. The fault location deviation is merely 1.36 m. The efficacy of this method in fault location is substantiated, which may serve as a reference for future research endeavors.

In this paper, a voltage-boost-type non-voltage drop single-phase full-bridge inverter connected to a switched-capacitor structure is proposed. The output voltage of the inverter is controlled by the pulse width modulation of a DSP to control the lead and break of the active switches. The full-bridge switches work at low frequency; the other switches work at high frequency. The inverter uses two capacitor modules to charge and discharge alternately so as to overcome the problem of voltage drop on the output side of the inverter in the transition stage from series capacitor discharge to parallel charge. By analyzing the charge–discharge characteristics of the RC charge–discharge circuit, the capacitor charge–discharge cycle can be adjusted to alter the output voltage within a certain range. The results from the physical construction verify the Simulation results achieved well, which demonstrates satisfactory performance that supports the verification of the above theory.

Rectifier is the most critical block of the power conditioning circuit designed for the Piezoelectric Energy Harvester (PZEH). Maintaining high rectification efficiency under the variable ambient conditions is the major design challenge. This paper presents a novel topology of self tuned Synchronized Switch Harvesting on Inductor (SSHI) based rectifier circuit for PZEH which provides high power extraction efficiency over a wide range of frequency and magnitude of input vibrations available. The high rectification efficiency is maintained for different PZ devices also. The synchronization of SSHI block under different ambient conditions is achieved by an adaptively controlled pulse generator circuit which uses internal voltage sensing. An active diode circuit to reduce the conduction loss in SSHI block and forward voltage drop of rectifier is used. The proposed circuit is working from 100 to 350 Hz with flipping efficiency above 90% and power extraction efficiency around 50%. A maximum power conversion efficiency of 58 % and maximum flipping efficiency of 93.6% is obtained with a figure of merit of 467% and output power of 72.6μW .