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A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first; by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state-of-the-art. The synthesis results over GF(2m) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex-7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.

The development of quantum computing architectures from early designs and current noisy devices to fully fledged quantum computers hinges on achieving fault tolerance using quantum error correction 1 – 4 . However, these correction capabilities come with an overhead for performing the necessary fault-tolerant logical operations on logical qubits (qubits that are encoded in ensembles of physical qubits and protected by error-correction codes) 5 – 8 . One of the most resource-efficient ways to implement logical operations is lattice surgery 9 – 11 , where groups of physical qubits, arranged on lattices, can be merged and split to realize entangling gates and teleport logical information. Here we report the experimental realization of lattice surgery between two qubits protected via a topological error-correction code in a ten-qubit ion-trap quantum information processor. In this system, we can carry out the necessary quantum non-demolition measurements through a series of local and entangling gates, as well as measurements on auxiliary qubits. In particular, we demonstrate entanglement between two logical qubits and we implement logical state teleportation between them. The demonstration of these operations—fundamental building blocks for quantum computation—through lattice surgery represents a step towards the efficient realization of fault-tolerant quantum computation. Two logical qubits are encoded in ensembles of four physical qubits through the surface code, then entangled by lattice surgery, which is a protocol for carrying out fault-tolerant operations.

Realizing a high-performance and energy-efficient circuit system is one of the critical tasks for circuit designers. Conventional researchers always concentrated on the tradeoffs between the energy and the performance in circuit and system design based on accurate computing. However, as video/image processing and machine learning algorithms are widespread, the technique of approximate computing in these applications has become a hot topic. The errors caused by approximate computing could be tolerated by these applications with specific processing or algorithms, and large improvements in performance or power savings could be achieved with some acceptable loss in final output quality. This paper presents a survey of approximate computing from arithmetic units design to high-level applications, in which we try to give researchers a comprehensive and insightful understanding of approximate computing. We believe that approximate computing will play an important role in the circuit and system design in the future, especially with the rapid development of artificial intelligence algorithms and their related applications.

The quantum-dot cellular automata (QCA) can be replaced to overcome the limitation of CMOS technology. An arithmetic logic unit (ALU) is a basic structure of any computer devices. In this paper, design of improved single-bit arithmetic logic unit in quantum dot cellular automata is presented. The proposed structure for ALU has AND, OR, XOR and ADD operations. A unique 2:1 multiplexer, an ultra-efficient two-input XOR and a low complexity full adder are used in the proposed structure. Also, an extended design of this structure is provided for two-bit ALU in this paper. The proposed structure of ALU is simulated by QCADesigner and simulation result is evaluated. Evaluation results show that the proposed design has best performance in terms of area, complexity and delay compared to the previous designs.

This study investigates the relationship between children’s subitizing activity and their construction of arithmetic units. In particular, the study hypothesizes a positive association between children’s construction of subitized units and their construction of arithmetic units, and hypothesizes that children who can subitize larger units, such as five items, in kindergarten, are more likely to construct arithmetic units by the beginning of first grade. Data for this study were drawn from 3,660 children surveyed at the beginning of kindergarten in 2014, 2015, and 2016, and at the beginning of first grade in the following year. The children are from a single school district in the southwest United States. Logistic regression was used to model the likelihood of constructing arithmetic units based on children’s earlier construction of subitized units. Findings provide evidence of a positive relationship between children’s construction of subitized units and arithmetic units, and, on average, children who have constructed subitized units at the beginning of kindergarten are more likely to construct arithmetic units by the beginning of first grade. Based on the findings, theoretical and instructional implications are discussed.

AbstractIn modern microprocessors, the arithmetic logic units (ALUs) with the accelerated transfer organization, which are faster than ALUs with the sequential organization of arithmetic transfer, are widely used to reduce time costs. However, as the input data capacity increases, the operating time of such ALUs increases linearly with an increase in the number of bits. Developing an efficient ALU to deliver better performance than the existing known solutions is a pressing challenge. In this study, ALUs with the sequential and accelerated organization of arithmetic transfer are analyzed. A multidigit ALU is developed to increase the operating speed. All the ALU schemes were modeled in the CAD Altera Quartus-II environment. The number of gates and the maximum delay in the ALU circuit simulation report are compared for 4, 8, 16, 32, and 64 bits. A results verification scheme is implemented to confirm the reliability of the developed ALU. It is found that when performing operations with 64-bit operands, the developed ALU reduces the maximum delay by 53% compared to ALUs with the sequential organization of the arithmetic transfer and by 35.5% compared to ALUs with the accelerated organization of the arithmetic transfer.

Objective: The need of a computer in the modern world is inevitable, whose sole purpose is to compute or aid calculations. The need for an Arithmetic Logic Unit (ALU) is as important as the computer, simply because ALU forms the fundamental part of any Central Processing Unit (CPU). And so the encryption of an ALU is highly mandatory for the safety of the device as there are hardly any device without an ALU

Gate diffusion input (GDI) method using a simple cell makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst-case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte Carlo procedure in standard 32 nm technology utilizing the Synopsys HSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible-based applications, such as future generations of FPGA chips and CNTFET-based computers.

Quantum computers require quantum processors. An important part of the processor of any computer is the arithmetic unit, which performs binary addition, subtraction, division and multiplication, however multiplication can be performed using repeated addition, while division can be performed using repeated subtraction. In this paper we present two designs using the reversible R3 gate to perform the quantum half adder/subtractor and the quantum full adder/subtractor. The proposed half adder/subtractor design can be used to perform different logical operations, such as AND, XOR, NAND, XNOR, NOT and copy of basis. The proposed design is compared with the other previous designs in terms of the number of gates used, the number of constant bits, the garbage bits, the quantum cost and the delay. The proposed designs are implemented and tested using GAP software.

The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with high-performance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements.