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Automated liberty characterization remains elusive for asynchronous cells whose feedback and multi‐output behaviour break monolithic flows. We introduce a partition and recomposition strategy that exercises loop‐free sub‐blocks with exhaustive four‐phase testbenches and recompose the resulting liberty snippets into sign‐off views. Applied to sense amplifier half buffers, the flow limits functional error to below , timing deviation to , and power error to 13– while retaining of pins. The approach eliminates bespoke scenarios, scales linearly with library size, and enables asynchronous circuits to integrate into electronic design automation sign‐off.

A paired T-element that assists in successfully controlling a dual-rail delay-insensitive asynchronous circuit system that implements multiple states containing acknowledge networks, that are interdependent, is presented. A T-element allows triggering of next-state actions concurrently with negation of its acknowledge input. However, this introduces a timing assumption that can cause system failure if it is violated. With little additional overhead, the paired T-element is designed to combine the functionality of two standard T-elements and allow adjacent reads to take place when there are inter-state dependencies. This component successfully overlaps advantages of the performance optimisation of the original T-element with the safety of the solution to this control scenario, making it an important element to be used in dual-rail delay-insensitive asynchronous circuit systems.

This seminal book presents a new logically determined design methodology for designing clockless circuit systems.The book presents the foundations, architectures and methodologies to implement such systems.

With clock rates beyond 1 GHz, the model of a system wide synchronous clock is becoming difficult to maintain; therefore, asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application. In the face of increased transient fault rates, robustness is a crucial property, and from a conceptual view, the so-called ldquodelay-insensitiverdquo asynchronous design approaches promise to be more robust than synchronous ones, since their operation does not depend on tight timing margins, and data are two-rail coded. A practical assessment of asynchronous designs in fault-injection (FI) studies, however, can rarely be found, and there is a lack of adequate methods and tools in this particular domain. Therefore, the objective of this work is 1) to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs, and 2) to experimentally compare the robustness of both synchronous and asynchronous designs. To this end, a synchronous 16-bit processor as well as its asynchronous (delay insensitive) equivalent are subjected to signal flips and delay faults. The results of over 489 million experiments are summarized and discussed, and a detailed discussion on the specific properties of the chosen asynchronous design style is given.

Contactless smart cards operate using power harvested through inductive coupling, which requires the use of extremely low‐power, supply‐tolerant digital architectures. This work presents a self‐timed RISC‐V RV32I microprocessor that replaces the global clock with an asynchronous finite state machine based on a handshake protocol. This control scheme naturally adapts to supply voltage fluctuations, reducing both average and peak power consumption while ensuring the microprocessor operates robustly under variable conditions. The microprocessor was fabricated using a CMOS process and was then compared with equivalent synchronous implementations.

The paper shows the methodologies of implementing a high-performance low-power logic control system designed with the use of standard languages like LD and SFC (according to the IEC61131-3 standard) directly in hardware utilizing FPGA devices. The essential idea is to convert the sequential sentences of a language to parallel computations and then map them to a dedicated hardware structure. The flexible graph-based method of language mapping is shown. It enables extracting control and data flow from language sentences. The direct hardware mapping technique enables building not only a high-performance structures but also a low-power implementations. All implementations retain a very short response time consisting of several clock cycles (from 3 to 7). The proposed low-power mapping strategies enable power saving up to 10 times while retaining processing performance. The obtained results are compared with a standard implementation using a benchmark program set. The paper is concluded with a comparison of the performance and energy consumption for the proposed implementation strategies.

As the demand for low‐power electronic products grows, asynchronous circuits are considered a good alternative for addressing power consumption issues. Applying dynamic voltage scaling (DVS) in asynchronous circuits can further improve their power efficiency. However, asynchronous circuits face challenges, such as performance analysis considering voltage, temperature, and process variations. This paper proposes a new statistical performance analysis model for asynchronous pipelines. This model can be applied to two different styles of asynchronous circuits. The results show that this model has reasonable accuracy on estimated mean delay (2% error on average) compared to detailed analysis carried out with low‐level Monte Carlo (MC) circuit simulations.

Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H.

This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic. In a monotonic asynchronous circuit, the intermediate and primary outputs exhibit similar signal transitions as the primary inputs during data and spacer application. The proposed asynchronous full adder ensures monotonicity for processing data and spacer, utilizing dual-rail encoding for inputs and outputs, and corresponds to return-to-zero (RtZ) and return-to-one (RtO) handshaking. The early output feature of the proposed full adder allows the production of sum and carry outputs based on the adder inputs regardless of the carry input when the spacer is supplied. When utilized in a ripple carry adder (RCA) architecture, the proposed full adder achieves significant reductions in design metrics, such as cycle time, area, and power, compared to existing IOM asynchronous full adders. For a 32-bit RCA implementation using a 28 nm CMOS technology, the proposed full adder outperforms an existing state-of-the-art high-speed asynchronous full adder by reducing the cycle time by 10.4% and the area by 15.8% for RtZ handshaking and reduces the cycle time by 9.8% and the area by 15.8% for RtO handshaking without incurring any power penalty. Further, in terms of the power-cycle time product, which serves as a representative measure of energy, the proposed full adder yields an 11.8% reduction for RtZ handshaking and an 11.2% reduction for RtO handshaking.

The full memristive network hardware features high density and excellent scalability. However, recent researches on the full memristive network have been limited to a single-layer network, due to the lack of effective and flexible communication between neurons. In this design, we demonstrate a neuromorphic core based on Ag/SiO 2 /Au threshold switching memristor, which has built-in asynchronous address event representation (AER) circuits to provide flexible communication between neurons. Since temporally sparse spikes are the medium of communication between neurons, the AER circuits are designed to transmit spikes serially which have been encoded with neurons’ addresses before transmission. With the asynchronous circuits design, the AER circuits will detect neurons’ output in real-time. To test the performance of the neuromorphic core, we designed a behavioral simulator for the neuromporphic core to simulate the liquid state machine (LSM) network, which achieves a 100% recognition rate in the free spoken digital dataset. The simulation results show that the neuromorphic core obtains 35 times higher performance than the CPU and 111 times higher energy efficiency than the GPU.