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An accurate indication that the bandgap voltage reference (BGR) circuit is settled on its nominal value is essential in analog or mixed signal systems. In this paper, a generic method for accurate bandgap voltage reference (BGR) Ready-Indication (RI) is proposed. A RI signal shows that the BGR operates correctly but also is used to enable PoR circuits when those employ the bandgap voltage to generate the required thresholds. In many low power applications, several systems are periodically switched on and off to save power and to increase battery life. In such systems, most circuits must remain off, while BGR is not in ready mode, saving battery energy. In other critical applications, the Ready-Indicator can ensure that critical systems can be set on and the reference voltage is within the operating range. In this paper, the introduced methodology is applied to different reference voltage generators. Initially, a BGR with Ready-Indication is presented extensively, including post-layout simulations results in 22 nm, while thereafter, the study of this method is extended in other BGR topologies. The universality of the proposed method is proved by verifying the operation in all the BGR topologies under study covering designs in 22 nm and 65 nm and with supply voltages 1.8 V, 1 V, 0.55 V.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

A new precision-aware subthreshold-based MOSFET voltage reference is presented in this paper. The circuit was implemented TSMC−40 nm process technology. It consumed 9.6 μW at the supply voltage of 1.2 V. In this proposed work, by utilizing subthreshold-based MOSFET instead of bipolar junction transistor (BJT), relatively lower power consumption was obtained in the design while offering comparable precision to that offered by its BJT counterpart. Through the proposed second-order compensation, it achieved the temperature coefficient (T.C.) of 3.0 ppm/°C in the TT corner case and a 200-sample Monte-Carlo T.C. of 12.51 ppm/°C from −40 °C to 90 °C. This shows robust temperature insensitivity. The process sensitivity of Vref without and with trimming was 2.85% and 0.75%, respectively. The power supply rejection (PSR) was 71.65 dB at 100 Hz and 52.54 dB at 10 MHz. The Figure-of-Merit (FOM) for the total variation in output voltage was comparable with representative BJT circuits and better than subthreshold-based MOSFET circuits. Due to low T.C., low process sensitivity, and simplicity of the circuit architecture, the proposed work will be useful for sensor circuits with stringent requirements or other analog circuits that require high precision applications.

Based on the standard 40 nm Complementary Metal Oxide Semiconductor (CMOS) process, a curvature compensation technique is proposed. Two low-voltage, low-power, high-precision bandgap voltage reference circuits are designed at a 1.2 V power supply. By adding IPTAT (positive temperature coefficient current) and ICTAT (negative temperature coefficient current) to the output resistance, the first-order compensation bandgap voltages can be obtained. Meanwhile, the third high-order compensation current is also superimposed on the same resistance. We make use of the collector current of the bipolar transistor to compensate for the nonlinear term of VBE. The simulation results show that TC (temperature coefficient) of the first circuit reference could be reduced from 29.1 × 10−6/°C to 5.71 × 10−6/°C over the temperature range of −25 to 125 °C after temperature compensation. The second one could be reduced from 17 × 10−6/°C to 5.22 × 10−6/°C.

This paper describes design and simulation results of the bandgap reference source in CMOS 28nm technology. Proposed bandgap reference utilizes DTMOS transistors for providing currents of negative and positive temperature coefficients and is equipped with various techniques for process variation minimization such as common centroid element design and user controlled trimming resistors. This circuit achieves temperature coefficient equal to -18.87 ppm/(°C) with temperature ranging from -20°C to 100°C at 1V power supply, occupies 0.38 mm2 of silicon area, and consumes 3.66 μW of power.

This paper presents a sub-1-V CMOS bandgap reference circuit with ultra-low power consumption, utilizing only 9 MOS transistors. The proposed circuit achieves nano-watt power consumption by biasing all transistors in the sub-threshold region. A three-branched configuration is utilized to create the bandgap voltage reference in the circuit. The proposed architecture generates CTAT and PTAT voltages without using any op-amp and BJT. In this circuit, the cascode structure are used to improve the line sensitivity (LS). In the proposed bandgap circuit, self-biased configuration is used without using an external bias circuitry. The first branch generates PTAT current and the second and third branches generate PTAT and CTAT voltages. The bandgap circuit is designed and simulated using Cadence in TSMC 0.18 μm CMOS technology. The results of post-layout simulation indicate that the bandgap voltage reference circuit generates a voltage reference of 644 mV, with a temperature coefficient (TC) of 78.5 ppm/°C within the temperature range of − 25 to 85 °C. The proposed circuit operates with a power supply of 0.9 V and consumes only 8.2 nW. Furthermore, the circuit exhibits a line sensitivity of 0.31%/V for power supply voltages ranging from 0.9 to 1.8 V. The Power Supply Ripple Rejection (PSRR) of the proposed circuit is about − 40 dB within the frequency range of 1–100 Hz.

This paper presents the design of the temperature sensor and analysis of different calibration methods. The main aspect of the analysis was optimization of the number and location of the measurement points needed to perform the calibration for a given accuracy. For this purpose, temperature sensors using proportional to the absolute temperature (PTAT) current and current controlled oscillator (CCO) have been designed in 180 nm technology. To reduce the sensitivity of the sensor to the supply voltage, the low dropout regulator (LDO) has been used. The bandgap circuit generates the stable reference voltage for the LDO and PTAT current for the CCO.

A 3.0 V bandgap reference (BGR) for battery management integrated circuit (BMIC) is presented, achieving a low temperature coefficient (TC) and a high power supply rejection ratio (PSRR). Precision is enhanced through two techniques: (1) a base current correction technique eliminates errors from the bipolar junction transistor (BJT) base current, and (2) a high-order temperature compensation circuit counteracts the inherent nonlinearity of the BJT's base-emitter voltage ( ). Furthermore, an improved flipped voltage follower (FVF) pre-regulation structure is integrated for efficient power supply noise suppression. The circuit is designed based on a 180 nm BiCMOS process, occupying a layout area of 0.0459 mm . Post-layout simulation results demonstrate that the BGR achieves a temperature coefficient of 1.59 ppm/°C over the -40 °C to 125 °C temperature range. Within a supply voltage range of 4.7 V to 5.3 V, the line regulation is 0.00058 mV/V. At a 5.0 V supply voltage, the quiescent current is 23 μA, and the PSRR is -128.89 dB@1 Hz and -102.9 dB@1 kHz.

To meet the requirements of integrated accelerometers for a high-precision reference voltage under wide supply voltage range, high current drive capability, and low power consumption, this paper presents a bandgap reference operational amplifier (op-amp) circuit implemented in CMOS/BiCMOS technology. The proposed design employs a folded-cascode input stage, a push–pull Class-AB output stage, an adaptive output switching mechanism, and a composite frequency compensation scheme. In addition, overcurrent protection and low-frequency noise suppression techniques are incorporated to balance low static power consumption with high load-driving capability. Simulation results show that, under the typical process corner (TT), with VDD = 3 V and T = 25 °C, the op-amp achieves an output swing of 0.2 V~2.8 V, a low-frequency gain of 102~118 dB, a PSRR of 90 dB at 60 Hz, overcurrent protection of ±25 mA, and a phase margin exceeding 48.8° with a 10 μF capacitive load. Across the entire supply voltage range, the static current remains below 150 μA, while maintaining a line regulation better than 150 μV/V and a load regulation better than 150 μV/mA. These results verify the feasibility of achieving both high drive capability and high stability under stringent power constraints, making the proposed design well-suited as a bandgap reference buffer stage for integrated accelerometers, with strong engineering practicality and potential for broad application.

This paper presents a resistor-less high-order curvature compensation bandgap voltage reference. A high-order curvature compensation is based on generating successive VGS voltages with different temperature characteristics, which are used to cancel thermal nonlinearity the first- and higher-order terms of the transistor voltage VEB. At the same time, a piecewise-linear curvature compensation circuit is used to broaden the temperature range of the whole circuit and achieve low-temperature coefficient. The proposed bandgap reference was designed using standard CSMC 0.18-μm CMOS technology. Simulation results indicate that the proposed bandgap reference achieves the best temperature coefficient of 2.37 ppm/°C from − 40 to 125 °C with a supply voltage of 5 V. The BGR output is about 1.1881 V and a − 60.7-dB PSRR at 10 kHz while only consuming 200 μW.