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Time–domain simulation of electronic and thermal circuits is required by a large array of applications, such as the design and optimization of electric vehicle powertrain components. While efficient execution is always a desirable feature of simulation codes, in certain cases like System-in-the-Loop setups, real-time performance is demanded. Whether real-time code execution can be achieved or not in a particular case depends on a series of factors, which include the mathematical formulation of the equations that govern the system dynamics, the techniques used in code implementation, and the capabilities of the hardware architecture on which the simulation is run. In this work, we present an evaluation framework of numerical methods for the simulation of electronic and thermal circuits from the point of view of their ability to deliver real-time performance. The methods were compared using a set of nontrivial benchmark problems and relevant error metrics. The computational efficiency of the simulation codes was measured under different software and hardware environments, to determine the feasibility of using them in industrial applications with reduced computational power.

In this work, we present a new four-dimensional chaotic hyperjerk system with a half-line of equilibrium points. In the chaos literature, it is well-known that chaotic systems with an infinite number of equilibrium points exhibit hidden attractors. Thus, we deduce in this research work that the new chaotic hyperjerk system has hidden attractors. We next study the new chaotic hyperjerk system for a dynamic analysis using bifurcation plots and Lyapunov Exponents (LE) diagrams.We exhibit that the new hyperjerk system has a special property of multistability with coexisting attractors. Using Multisim version 14.2, we carry out an electronic circuit simulation for the proposed 4-D chaotic hyperjerk system with a half-line of equilibrium points. Finally, as an application in control engineering, we apply backstepping control for achieving antisynchronization of a pair of new chaotic hyperjerk systems taken as master-slave systems, which has important applications in communication systems.

Excessive power supply noise (PSN) such as IR drop can cause yield loss when testing very large scale integration chips. However, simulation of circuit timing with PSN is not an easy task. In this study, the authors predict circuit timing for all test patterns using three machine learning techniques, neural network (NN), support vector regression (SVR), and least-square boosting (LSBoost). To reduce the huge dimension of raw data, they propose four feature extractions: input/output transition (IOT), flip-flop transition in window (FFTW), switching activity in window (SAW), and terminal FF transition of long paths (PATH). SAW and FFTW are physical-aware features while PATH is a timing-aware feature. Their experimental results on leon3mp benchmark circuit (638 K gates, 2 K test patterns) show that, compared with the simple IOT method, SAW effectively reduced the dimension by up to 472 times, without significant impact on prediction accuracy [correlation coefficient = 0.79]. Their results show that NN has best prediction accuracy and SVR has the least under-prediction. LSBoost uses the least memory. The proposed method is more than six orders of magnitude faster than traditional circuit simulation tools.

Different types of capacitors have different parameters, e.g. equivalent series resistance (ESR) and capacitance. In switching DC–DC converters with voltage-mode (VM) hysteretic control, the output capacitor ESR has a significant effect on dynamic performance. In this reported work, two critical conditions of the output capacitor ESR for mode shifting and normal operation of the VM hysteretic controlled buck converter are derived. These results, verified by circuit simulations, illustrate that the larger output capacitor ESR is necessary for the converter operating normally; otherwise, the converter operates abnormally.

The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed.

A circuit simulator is a computer program that permits us to see circuit behavior, i.e. circuit voltages and currents, without making the circuit. Use of a circuit simulator is a cheap, efficient, and safe way to study the behavior of circuits. The Toolkit for Interactive Network Analysis (TINA®) is a powerful yet affordable SPICE based circuit simulation and PCB design software package for analyzing, designing, and real time testing of analog, digital, VHDL, MCU, and mixed electronic circuits and their PCB layouts. This software was created by DesignSoft. TINA-TI is a spinoff software program that was designed by Texas Instruments (TI®) in cooperation with DesignSoft which incorporates a library of pre-made TI components to for the user to utilize in their designs. This book shows how a circuit can be analyzed in the TINA-TI® environment. Students of engineering (for instance, electrical, biomedical, mechatronics and robotics to name a few), engineers who work in industry and anyone who want to learn the art of circuit simulation with TINA-TI can benefit from this book.

Microwave circuit simulation has always posed particular difficulties especially in highly non-linear applications because of the presence of distributed or electromagnetic structures, which are usually passive and linear, but difficult to incorporate effectively in time-domain analysis. A variety of specialised techniques has evolved to cope with this situation with reasonable success. In recent years, microwave systems are becoming more integrated and complex and often involve ‘mixed-signals’ that may operate over a very wide range of time scales, creating new simulation challenges. This study reviews the issues involved and suggests a practical paradigm for generalised time-domain simulation of microwave circuits.

In this letter, a novel true random number generator (TRNG) with high energy‐efficient and throughput is proposed for cryptographic systems. The current starve based ring oscillator (CSRO) is biased in the subthrehold region as an entropy source. An individual ring oscillator (RO) is sampled using multiple sampling points of the CSRO working in the sub‐threshold region to obtain a multi‐channel sequence output, thereby fully exploiting the randomness of the entropy source. The proposed TRNG is implemented using a standard 40nm CMOS technology and the simulation results show that it provides high‐quality and 20.66 Mbps random sequences while only consuming 11.46 μW at 1.1 V, 25°C. In addition, the proposed TRNG passes the NIST SP 800‐22 and the NIST SP 800‐90B tests without post‐processing and outperforms the state‐of‐the‐art in terms of energy consumption per bit of the output bitstream, reaching 0.555pJ/bit. In this letter, we proposed a novel true random number generator (TRNG) based on multi‐stage sampling of the current starve‐based ring oscillator (CSRO) to reduce the power consumption per bit of the output binary sequence. The simulation results show that it provides high‐quality and 20.66 Mbps random sequences while only consuming 11.46 μW at 1.1 V, 25°C which means its energy consumption per bit reaches 0.555pJ/bit, much lower than existing conventional design. The proposed TRNG also passes the NIST 800‐22 and NIST SP 800‐90B tests.

In this paper, a hyperchaotic memristive circuit based on Wien-bridge chaotic circuit was designed. The mathematical model of the new circuit is established by using the method of normalized parameter. The equilibrium point and the stability point of the system are calculated. Meanwhile, the stable interval of corresponding parameter is determined. Using the conventional dynamic analysis method, the dynamical characteristics of the system are analyzed. During the analysis, some special phenomenon such as coexisting attractor is observed. Finally, the circuit simulation of system is designed and the practical circuit is realized. The results of theoretical analysis and numerical simulation show that the Wien-bridge hyperchaotic memristive circuit has very rich and complicated dynamical characteristics. It provides a theoretical guidance and a data support for the practical application of memristive chaotic system.

A novel 5 GS/s highly linear voltage‐scalable voltage‐to‐time converter (VTC) has been presented for the time‐domain (TD) ADCs. The proposed VTC employs an innovative sample‐and‐hold (S/H) network to scale the sampled voltage, extending the input voltage range while overcoming the trade‐off between linearity and input range that has been a limitation of conventional VTCs. In addition, this work introduces an enhanced bootstrapped switch to improve linearity when handling high‐frequency input signals. The proposed VTC is designed in the 28 nm CMOS process, occupying an area of 972 μm2 $\\mu{\\rm m}^2$ . Post‐layout simulation results demonstrate that, with an input voltage of 1.4 Vpp,diff ${\\rm V}_{\\text{pp}, \\text{diff}}$ , the VTC achieves a total harmonic distortion (THD) of −62.9 dB and a spurious‐free dynamic range (SFDR) of 65.5 dB for Nyquist input, while consuming only 1.92 mW of power. A novel 5 GS/s highly linear voltage‐scalable voltage‐to‐time converter (VTC) has been presented for the time‐domain (TD) ADCs. The proposed VTC employs an innovative sample‐and‐hold (S/H) network to scale the sampled voltage, extending the input voltage range while overcoming the trade‐off between linearity and input range that has been a limitation of conventional VTCs. In addition, this work introduces an enhanced bootstrapped switch to improve linearity when handling high‐frequency input signals.