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The surveillance cameras we focus on target the volume zone, and area reduction is a top priority. However, by simplifying the ADC comparator, we face a new RUSH current issue, for which we propose a circuit solution. This paper proposes two novel techniques of column-ADC for surveillance cameras to improve low-light characteristics. RUSH current compensation reduces transient current consumption fluctuations during AD conversion and utilizing timing shift ADCs decreases the number of simultaneously operating ADCs. These proposed techniques improve low-light characteristics because they reduce the operating noise of the circuit. In order to support small signal measurement, this paper also proposes a high-accuracy evaluation system that can measure both small optical/electrical signals in low-light circumstances. To demonstrate these proposals, test chips were fabricated using a 55 nm CIS process and their optical/electrical characteristics were measured. As a result, low-light linearity as optical characteristics were reduced by 63% and column interference (RUSH current) as an electrical characteristic was also reduced by 50%. As for the high-accuracy evaluation system, we confirmed that the inter-sample variation of column interference was 0.05 LSB. This ADC achieved a figure-of-merit (FoM) of 0.32 e-·pJ/step, demonstrating its usefulness for other ADC architectures while using a single-slope-based simple configuration.

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC’s linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

This paper proposes a readout design for CMOS image sensors. It has been squeezed into a 7.5um pitch under a 0.28um 1P3M technology. The ADC performs one 14-bit conversion in only 1.5us and targets a theoretical DNL feature about +1.3/-1 at 14-bit accuracy. Correlated Double Sampling (CDS) is performed both in the analog and digital domains to preserve the image quality.