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An MMC is widely applied to the HVDC power transmission system. With a large number of insulated gate bipolar transistors (IGBTs) utilized in MMC-HVDC converter stations, an extremely complicated EM environment is generated due to the dv/dt and di/dt during the IGBT switching process. A magnetic field simulation model is proposed to calculate the magnetic field generated by a 4.5 kV/5 kA IGBT-based MMC submodule under the DPT, with the dynamic switching behavior of IGBTs considered. Firstly, a behavior model of 4.5 kV/5 kA IGBTs is built with the help of commercial software. To validate its effectiveness, a DPT simulation model is built. A comparison between the simulation result and the measured data is performed. Finally, a quasi-static Maxwell model is utilized to approximate the near field caused by the current Ic of the DPT. The simulation result of the magnetic field strength at the point near the gate driver PCB is verified by the measurement data. The proposed magnetic field simulation model can help to analyze the EMI behavior and EMI design for MMC-HVDC submodules under DPT.

This study aims to investigate the influence of parasitic capacitances within half-bridge SiC power metal oxide semiconductor field effect transistor (MOSFET) modules, including input capacitance (Ciss), output capacitance (Coss), and reverse transfer capacitance (Crss), on their switching transients and switching losses during dynamic switching. A secondary objective is to assess the impact of parasitic capacitances on power loss and thermal performance in a single-phase SiC MOSFET inverter operating in an H-bridge configuration that employs two half-bridge SiC power MOSFET modules identical to the one described above. To accurately capture the switching transients, switching losses, and parasitic effects of the SiC power module during dynamic transients and inverter operating under sinusoidal pulse-width modulation (SPWM) in single-phase open-loop mode, an electromagnetic-circuit modeling (EMCM) framework is developed. This approach integrates an electromagnetic model, an equivalent circuit model, and a SiC MOSFET characteristic model. The validity of the proposed integrated modeling framework is verified by comparison with the measurement results obtained from double-pulse testing (DPT) and thermal resistance experiments. Ultimately, using the developed integrated modeling framework, a guideline for improving power loss and thermal behavior of the power inverter under various device and system conditions is formulated through parametric analysis. The findings demonstrate that parasitic capacitances significantly affect switching waveforms and loss, and also influence the thermal performance of the system, with Crss showing the most dominant impact.

The Gallium Nitride high electron mobility transistor (GaN HEMT) has been considered as a potential power semiconductor device for high switching speed and high power density application since its commercialization. Compared with the traditional Si transistors, GaN HEMT has faster switching speed and lower on-off loss. As a result, it is more sensitive to the nonlinear parameters due to the fast switching speed. The subsequent voltage and current overshooting will affect the efficiency and safety of the GaN HEMT and power electronic systems. In this paper, an accurate switching transient analytical model for GaN HEMT is proposed, which considers the effects of parasitic inductances, nonlinear junction capacitances and nonlinear transconductance. The model characteristic of turn-ON process and turn-OFF process is illustrated in detail, and the equivalent circuits are derived for each switching transition. The accuracy of the proposed model can be verified by comparing the predicted switching waveform and switching loss with that of the experimental results based on the double pulse test (DPT) circuit. Compared with the conventional model, the proposed model is more accurate and matches better with the experimental results than the conventional model. Finally, this model can be used for analyzing the influences of gate resistance, nonlinear junction capacitances, and parasitic inductances on switching transient waveform and refining calculation switching loss.

This work is dedicated to the practical determination and comparison of the dynamic characteristics of silicon (Si) MOSFET, silicon carbide (SiC) MOSFET, and silicon IGBT when switching an active-inductive load, which is the most used mode of operation in electric drives and power converters. The main advantages and challenges associated with the use of high-speed switches in real applications are discussed. The methodology of the Double-Pulse Test (DPT), a widely used method for experimental determining the dynamic characteristics of MOSFET and IGBT is presented. An experimental setup for conducting this test was designed and manufactured. The transistors were tested under identical voltage conditions for different switching currents. The analysis of the experimental data has demonstrated that, under equal conditions, SiC-MOSFET provides the lowest switching losses, making it the most suitable for applications which demand high-frequency PWM. It is shown that due to the lowest turn-on and turn-off delays (compared to other types of transistors considered) SiC-MOSFET can potentially reduce the converter's dead-time, this fact, in turn, improves the inverter's dynamic performance and simplifies or even eliminates the need for dead-time compensation algorithms. References 27, figures 13, tables 3.

This paper compares the static and dynamic performance of 1.2 kV 4H-SiC ACCUFETs and INVFETs with identical channel length (0.5 μm) and gate oxide thickness (55 nm). It is demonstrated for the first time that ACCUFETs have lower total switching losses in comparison to the INVFETs. ACCUFETs are therefore superior devices for applications due to their lower specific on-resistance and overall switching losses. However, short circuit tests conducted on the devices show that ACCUFETs have a smaller short-circuit time (tSC) in comparison the INVFETs due to their higher short-circuit current.

Gallium nitride (GaN) devices are advantageous over conventional Silicon (Si) devices in terms of their small size, low on-resistance, and high dv/dt characteristics; these ensure a high integrated density circuit configuration, high efficiency, and fast switching speed. Therefore, in the diagnosis and protection of a system containing a GaN power semiconductor, the transient state for accurate switch current measurement must be analyzed. The pick-up coil, as a current sensor for switch current measurement in a system comprising a surface-mount-device-type nonmodular GaN power semiconductor, has the advantages of a higher degree-of-freedom configuration for its printed circuit board, a relatively small size, and lower cost than other current sensors. However, owing to the fast switching characteristics of the GaN device, a bandwidth of hundreds MHz must be secured along with a coil configuration that must overcome the limitations of relatively low sensitivity of the conventional current sensor. This paper analyzes the pick-up coil sensor models that can achieve optimal bandwidth and sensitivity for switch current measurement in GaN based device. So four configurable pick-up coil models are considered and compared according to coil-parameter using mathematical methods, magnetic, and frequency-response analysis. Finally, an optimal coil model is proposed and validated using a double-pulse test.

Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have many advantages compared to silicon (Si) MOSFETs: low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency. As a result, Si MOSFETs are replaced with SiC MOSFETs in many industrial applications. However, there are still not as many SiC modules to customize for each application. To meet the high-power requirement for custom applications, paralleling discrete SiC MOSFETs is an essential solution. However, it comes with many technical challenges; inequality in current sharing, different switching losses, different transient characteristics, and so forth. In this paper, the detailed MATLAB®/Simulink® Simpscape model of the SiC MOSFET from the datasheet and the simulation of the half-bridge circuit are investigated. Furthermore, this paper proposes the implementation of the four-paralleled SiC MOSFET half-bridge circuit with an improved symmetric gate driver layout. Moreover, a unique laminated busbar connected directly to the printed circuit board (PCB) is proposed to increase current and thermal capacity and decrease parasitic effects. Finally, the experimental and simulation results are presented using a 650 V SiC MOSFET (CREE) double-pulse test (DPT) circuit. The voltage overshoot problems and applied solutions are also presented.

GaN-based power semiconductors exhibit small on-resistance and high dv/dt of the switch characteristics, thereby enabling the construction of high-efficiency, high-density semiconductor systems with fast switching and low power loss characteristics and miniaturization of passive devices. However, owing to the characteristics of GaN devices that result in them being significantly faster than other devices, the accuracy of the switching transient response significantly affects the noise or inductance in the device. Therefore, securing sufficient sensor bandwidth is considerably important for accurate current measurement in GaN-based devices. Conversely, the current sensor in the form of a non-insulated coil must secure sufficient bandwidth and overcome the tradeoff relationship with measurement sensitivity; moreover, the sensor configuration must be applicable to various power semiconductor types. This study proposes a current sensor model that applies the principle of the printed circuit board Rogowski coil to a surface mount device-type GaN-based half-bridge structure. This structure is applicable to a nonmodular power converter and is designed to secure sufficient bandwidth with a minimum area while simultaneously exhibiting high sensitivity. For the coil design, mutual inductances with existing coil structures were compared and analyzed, and the frequency response and magnetic analysis were evaluated. Experimental verification was performed and the transient response characteristics in various DC voltage ranges are discussed.

Dynamic on-resistance (RON) of commercial GaN on Si normally off high-electron-mobility transistor (HEMT) devices is a very important parameter because it is responsible for conduction losses that limit the power conversion efficiency of high-power switching converters. Due to charge trapping effects, dynamic RON is always higher than in DC, a behavior known as current collapse. To study how short-time dynamics of charge trapping and release affects RON we use rectangular 0–5 V gate voltage pulses with durations in the 1 μs to 100 μs range. Measurements are first carried out for single pulses of increasing duration, and it is found that RON depends on both pulse duration and drain current ID, being higher at shorter pulse durations and lower ID. For a train of five pulses, RON decreases with pulse number, reaching a steady state after a time interval of 100 μs. The response to a five pulses train is compared to that of a square-wave signal to study the time evolution of RON toward a dynamic steady state. The DC RON is also measured, and it is a factor of ten smaller than dynamic RON at the same ID. This confirms that a reduction in trapped charges takes place in DC as compared to the square-wave switching operation. Additional off-state stress tests at VDS = 55 V reveal the presence of residual surface traps in the drain access region, leading to four times increase in RON in comparison to pristine devices. Finally, the dynamic RON is also measured by the double-pulse test (DPT) technique with inductive load, giving a good agreement with results from single-pulse measurements.

The dynamic on-resistance (RON) behavior of one commercial GaN HEMT device with p-GaN gate is investigated under hard-switching conditions. The non-monotonic performance of dynamic RON with off-state voltage ranging from 50 to 400 V is ascribed to the “leaky dielectric” model. The highest normalized RON value of 1.22 appears at 150 and 200 V. The gradual increase and following maximum of dynamic RON are found when the device is exposed to a stress voltage for an extended stress time under 100 and 200 V, which is due to a much longer trapping time compared to detrapping time related to deep acceptors and donors. No obvious RON degradation, thanks to the suppressed trapping effect, is observed at higher VDS. From the multi-pulse test, the dynamic RON is seen to be insensitive to the frequency. It is demonstrated that the leakage, especially under source and drain contact, is a key issue in the dynamic resistance degradation.