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The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.

K‐means clustering is a machine learning algorithm used to group the data based on the similarity between the data. Functional distances like squared Euclidean distance, city block, cosine, correlation and hamming are considered as a similarity parameter here. Test vectors are grouped based on the functional distance using the K‐means algorithm. A simple reordering algorithm is proposed and is applied to each group of data before ‘X’ bit filing to minimize the test power. Experimental results on ISCAS 89 benchmark circuit shows that the proposed methods diminish the power effectively.

This letter presents a non‐linear dynamic behaviour model for characterising the broadband power amplifiers (PAs) by using deep convolution generative adversarial networks (DCGAN). The DCGAN structure is based on the convolution neural network model and combines the generative adversarial networks to improve its linearisation ability of the digital predistortion. The DCGAN contains a generation model and a discriminant model. It imports convolution with steps and deconvolution into the structure, respectively, which makes the accuracy of the power amplifier non‐linear model to improve further. For verification, a 5G NR test signal with 100 MHz bandwidth is employed for testing a Doherty RF‐PA that operates at 1800 MHz. The experimental results illustrate that the normalised mean square error value is at least 12 dB higher than the traditional models, and the out‐of‐band suppression of the DCGAN predistorter can be up to 15 dB better than other models.

In microwave device and circuit design, many simulations are often needed to find a set of designs that satisfy one or multiple specifications chosen by the designer upfront: the feasible region. A novel Bayesian active learning framework is presented to accurately identify the feasible region with a low number of simulations. The technique leverages on a stochastic model to obtain an efficient and automated procedure. A suitable application example validates the proposed technique and shows its effectiveness to rapidly obtain many suitable designs.

Gallium nitride based high‐power electronic devices are now in full swing. However, the phenomenon that the gallium nitride Schottky diodes break down prematurely without reaching the gallium nitride material limit is unsolved. This paper proposes a novel hybrid termination structure for vertical gallium nitride Schottky diodes to improve breakdown voltage. This work is carried out to simulate the breakdown voltage and reverse characteristics of the vertical gallium nitride Schottky diode by using technology computer aided design (TCAD) simulation. Under the same testing conditions, we demonstrate that compared with the control vertical Schottky diode, the breakdown voltage of the proposed Schottky diode can be significantly advanced, which has increased by 350 V and reached 850 V.

Dynamic thermal management (DTM) is applied to address the thermal problem of high performance very‐large‐scale integrated chips. The false alarm rate (FAR) can be used to evaluate the impact of full‐chip thermal field reconstruction accuracy on DTM. A low FAR relies on the accurate reconstruction of the full thermal field, especially near the temperature triggering threshold of DTM. However, little attention is currently being paid to such temperature ranges. To reduce FAR, a new full‐chip thermal field reconstruction strategy is proposed. A low‐dimensional linear model is used to accurately represent the thermal fields. The dictionary learning technology is exploited to train the model and the minimum weighted mean square error evaluation method is incorporated to improve the reconstruction accuracy near the temperature triggering threshold. A temperature sensor placement algorithm using the heuristic algorithm to solve the NP‐hard problem is also proposed. The experimental results show that the proposed strategy can reconstruct the full thermal field with a more precise accuracy near the triggering threshold and achieve the lowest FAR compared to the state of the art.

This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics. This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events) – this is best employed on the dedicated hardware. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper also shows how event‐based computing has been employed to solve certain computing problems orders of magnitude more quickly than the equivalent traditional big computing approach.

The conventional computing system has been facing enormous pressure to cope with the uprising demand for computing speed in today's world. In search of high-speed computing in the nano-scale era, it becomes the utmost necessity to explore a viable alternative to overcome the challenges of the physical limit of complementary-metal-oxide-semiconductor (CMOS). Towards that direction, the processing-in-memory (PIM) is advancing its importance as it keeps the computation as adjacent as possible to memory. It promises to outperform the latencies of the conventional stored-program concept by embedding storage and data computation in a single unit. On the other hand, the bit storing and processing capability of Akers array provides the foundation of PIM. Again, quantum-dot cellular automata (QCA) emerges as a promising nanoelectronic to put back CMOS to give fast-paced devices at the nanoelectronics era. This work presents a novel PIM concept, embedding Akers array in QCA to achieve high-speed computing at the nano-scale era. QCA implementation of universal logic utilizing Akers array signifies its processing power and puts forth its potentials. A universal function is considered for testing the effectiveness of the proposed PIM cell. The performance evaluation indicates the efficacy of QCA PIM over the conventional Von Neumann architecture.

The merit of higher order functions for hardware description and transformation is widely acknowledged by hardware designers. However, the use of higher order types makes their correctness proof very difficult. Herein, a new proof approach based on the principle of partial application is proposed which transforms higher order functions into partially applied first‐order ones. Therefore, parameterised architectures modelled by higher order functions could be easily redefined only over first‐order types. The proof could be performed by induction within the same specification framework that avoids translating the higher order properties between different semantics, which remains extremely difficult. Using the notion of parameterisation where verified components are used as parameters to build more complex ones, the approach fits elegantly in the incremental bottom‐up design where both the design and its proof could be developed in a systematic way. The potential features of the proposed methodological proof approach are demonstrated over a detailed example of a circuit design and verification within a functional framework.

An augmented radial basis function neural network (ARBFNN) is proposed for modelling and linearising a wideband Doherty power amplifier (DPA) with strong memory effects and static nonlinearity. To evaluate the performance of the ARBFNN, a 51 dBm DPA and a 25 MHz mixed test signal were used in modelling and linearisation measurement. Compared with the memory polynomial (MP) model and the real-valued time-delay neural network (RVTDNN), the ARBFNN is highly effective, leading to 3 and 5 dB improvements in the normalised mean square error. More importantly, the ARBFNN predistorter represents a significant improvement over the RVTDNN and MP in the suppression of the out-of-band spectral regrowth. In addition, the ARBFNN has a similar linearisation capability as the generalised MP model, but has much better numerical stability.