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In this paper, a fast-transient-response NMOS low-dropout regulator (LDO) with a wide load-capacitance range was presented to provide a V/2 read bias for cross-point memory. To utilize the large dropout voltage in the V/2 bias scheme, a fast loop consisting of NMOS and flipped voltage amplifier (FVA) topology was adopted with a fast transient response. This design is suitable to provide a V/2 read bias with 3.3 V input voltage and 1.65 V output voltage for different cross-point memories. The FVA-based LDO designed in the 110 nm CMOS process remained stable under a wide range of load capacitances from 0 to 10 nF and equivalent series resistance (ESR) conditions. At the capacitor-less condition, it exhibited a unity-gain bandwidth (UGB) of approximately 400 MHz at full load. For load current changes from 0 to 10 mA within an edge time of 10 ps, the simulated undershoot and settling time were only 144 mV and 50 ns, respectively. The regulator consumed 70 µA quiescent current and achieved a remarkable figure-of-merit (FOM) of 1.01 mV. At the ESR condition of a 1 µF off-chip capacitor, the simulated quiescent current, on-chip capacitor consumption, and current efficiency at full load were 8.5 µA, 2 pF, and 99.992%, respectively. The undershoot voltage was 20 mV with 800 ns settling time for a load step from 0 to 100 mA within the 10 ps edge time.

Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output power transistor, this LDO can quickly adjust the gate voltage of the power transistor without additional power consumption. By adding an active capacitor circuit composed of a fast comparator with offset voltage at the output point, this LDO can quickly charge/discharge the transient current and accelerate the transient response without reducing the circuit stability. Simulation results show that the proposed LDO has an output voltage of 1.8 V, when the input voltage is 2 V to 5 V while consuming 66.4 μA of quiescent current. The proposed capless LDO has a 1.94 µV/mA load regulation, a 0.55 mV/V linear regulation, and a −60 dB@1 kHz power supply rejection. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO settles in 400 ns with an overshoot and undershoot of 67 mV and 86 mV, respectively.

This paper presents a fast transient response low-dropout (LDO) regulator with all-NPN push–pull buffer in 0.6-μm bipolar process. In order to improve the transient response, an all-NPN push–pull buffer is proposed. Based on single Miller capacitance (SMC), the use of the all-NPN push–pull buffer overcomes the shortcomings of the equivalent series resistance (ESR) that requires strict output capacitor types. Besides, the proposed merging structure of bandgap reference and error amplifier not only improves the transient response, but also simplifies the circuit and reduces the output noise. Implemented and fabricated in a 0.6-μm bipolar process, the proposed LDO regulator occupies an active area of 1.6 mm 2 . The measured maximum load current is 200 mA, and the circuit can work at the load current of 300 mA. Moreover, the measured line regulation and load regulation are 0.8 mV/V and 0.09 mV/mA, respectively.

The Buck converter is a commonly used voltage regulator (VR) structure that supplies power to the load devices and responds to load transients. In most of the applications, the VR is controlled by voltage or current mode control, and some nonlinear approaches are used to improve the transient response which brings more complexities to the closed loop design. To achieve a fast transient response without over-regulation under a load step transient, this paper proposes a digital single-cycle regulation (SCCR) controller, which comprised a fast path, a slow path, and a neutralization path. Unlike the conventional PID control, the neutralization path of the SCCR controller is used to offset the excessive energy change in the first cycle after a load step occurs, which makes the inductor current reach its new static condition in a shorter period of time. The mathematical model of the SCCR control is established in this paper and a scanning algorithm is proposed for the design of the compensator parameters. Experimental results are presented to verify the improvement of the transient response when compared to the conventional and nonlinear PID control, the recovery time is decreased by 64.3% and 43% for load step-up and step-down when compared with nonlinear PID control.

This study investigates the evolution of axial loads in the secondary air system following shaft failure in aeroengines. It addresses a significant gap in the existing literature regarding the effects of inertial forces within the cavity, as well as the unclear mechanisms by which the geometric parameters of the flow path influence these forces. A combined approach of three-dimensional simulation and experimental validation is utilized to propose a method for analyzing the evolution of axial loads during the fast transient response process, based on changes in the Cavity Inertial Force Dominant Zone (CIDZ). The research examines both single cavities and cavity–tube combination flow paths to explore the impact of inertial forces on the axial load response process and, subsequently, the influence of flow path geometric parameters on this response. The results demonstrate that inertial forces within the cavity and the geometric parameters of the flow path significantly affect the axial load response process by influencing the intensity, phase, and minor oscillation amplitude of the axial load response at various end faces within the cavity. The variation in a single geometric parameter in this study resulted in a maximum impact exceeding 500% on the differences in axial loads at different end faces within the cavity. The study offers theoretical support for the load response analysis of the secondary air system in the context of shaft failure, serving as a foundation for safety design related to this failure mode.

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm2 in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works.

In this paper, output capacitor-less low-dropout (LDO) regulator using active-feedback and current-reuse feedforward compensation (AFCFC) is presented. The open-loop transfer function was obtained using small-signal modeling. The stability of the proposed LDO was analyzed using pole-zero plots, and it was confirmed by simulations that the stability was ensured under the load current of 50 mA. The proposed compensation method increases gain-bandwidth product (GBW) and reduces the on-chip compensation capacitor. The proposed AFCFC technique was applied to a three-stage output capacitor-less LDO. The LDO has a GBW of 5.6 MHz with a small on-chip capacitor of 2.6 pF. Fast-transient time of 450 ns with low quiescent current of 65.8 μA was achieved. The LDO was fabricated in 130 nm CMOS process consuming 180 × 140 μm2 of the silicon area.

A new method to construct a discrete-time variable-structure repetitive controller for a class of linear systems perturbed by multiple-period exogenous signals is presented. The proposed control scheme combines the features of the discrete-time multiple-period repetitive control (MP-RC) and variable-structure control (VSC) techniques. The MP-RC part is assigned to simultaneously track and reject periodic signals consisting of multiple uncorrelated fundamental frequencies. The VSC part is then integrated to provide a fast transient response and robustness against plant parameter variations. Stability and robustness analyses are also elaborated to ensure that the resulting closed-loop system satisfies the desired control objectives. Moreover, it is shown through an example that the repetitive control system constructed using the proposed control method can effectively track a sinusoidal reference signal despite the presence of a multiple-period disturbance.

A low-dropout linear regulator (LDO) without external capacitors is designed, combining ultra-low power consumption and ultra-fast transient response. The common support voltage of the LDO is 2.5 V to 3.6 V with a stable output voltage of 1.2 V and an output current dynamic range of 10 μA to 20 mA to supply power to other circuit modules. A Rail-to-Rail Input-Output (RRIO) Class AB push-pull output amplifier and a dynamic bias circuit are also designed. Meanwhile, a dynamic bias circuit which can regulate the operating current of error amplifier is proposed by monitoring output voltage variation in order to provide a larger compensation current to the operational amplifier when the load current changes are at high frequency and maintain ultra-low operating current at low clock frequency. The LDO is designed without resistors, and the deep well NMOS is applied in the output stage in order to reduce the difficulty of loop compensation. Designed in a 180 nm CMOS process, the post-simulation results show that under the condition of 40 °C and 3 V input voltage, the static power consumption is 31.7 nA with a settling time (±5%) of less than 35 ns.

The LCL-type dual active bridge (LCL-DAB) DC-DC converter is a promising part for DC micro-grids due to its high voltage gain and low bridge current, but the issues of backflow power elimination and transient response optimization deserve attention in its operation. In this article, a virtual direct current control (VDCC) method of the LCL-DAB converter for fast transient response and no backflow power is proposed, which can eliminate the backflow power and improve the transient response against the input voltage and load disturbances. With dual-phase-shift (DPS) modulation scheme, the voltage-current characteristics are first analyzed using the phasor method. The small-signal mathematic model of the LCL-DAB converter is then established. The power characteristic is derived so the design regions of no backflow power can be graphed. On this basis, an appropriate outer phase shift ratio can be estimated to ensure a wide range of no backflow power operation. Moreover, a virtual voltage is generated to compensate in the control loop, thus the transient response against disturbances of the LCL-DAB converter can be improved under no backflow power. Simulation and prototype experimental results are presented to verify the feasibility of the proposed VDCC method.