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In principle, the recently proposed capacitive-coupling impedance spectroscopy (CIS) has the capability to acquire frequency spectra of complex electrical impedance sequentially on a millisecond timescale. Even when the measured object with time-varying unknown resistance Rx is capacitively coupled with the measurement electrodes with time-varying unknown capacitance Cx, CIS can be measured. As a proof of concept, this study aimed to develop a prototype that implemented the novel algorithm of CIS and circuit parameter estimation to verify whether the frequency spectra and circuit parameters could be obtained in milliseconds and whether time-varying impedance could be measured. This study proposes a dedicated processor that was implemented as field-programmable gate arrays to perform CIS, estimate Rx and Cx, and their digital-to-analog conversions at a certain time, and to repeat them continually. The proposed processor executed the entire sequence in the order of milliseconds. Combined with a front-end nonsinusoidal oscillator and interfacing circuits, the processor estimated the fixed Rx and fixed Cx with reasonable accuracy. Additionally, the combined system with the processor succeeded in detecting a quick optical response in the resistance of the cadmium sulfide (CdS) photocell connected in series with a capacitor, and in reading out their resistance and capacitance independently as voltages in real-time.

The JUNGFRAU 4‐megapixel (4M) charge‐integrating pixel‐array detector, when operated at a full 2 kHz frame rate, streams data at a rate of 17 GB s−1. To operate this detector for macromolecular crystallography beamlines, a data‐acquisition system called Jungfraujoch was developed. The system, running on a single server with field‐programmable gate arrays and general‐purpose graphics processing units, is capable of handling data produced by the JUNGFRAU 4M detector, including conversion of raw pixel readout to photon counts, compression and on‐the‐fly spot finding. It was also demonstrated that 30 GB s−1 can be handled in performance tests, indicating that the operation of even larger and faster detectors will be achievable in the future. The source code is available from a public repository. A new data acquisition and real‐time image analysis system with FPGAs and GPUs for kilohertz macromolecular crystallography applications is presented.

Aims The open‐loop nature of conventional deep brain stimulation (DBS) produces continuous and excessive stimulation to patients which contributes largely to increased prevalence of adverse side effects. Cerebellar ataxia is characterized by abnormal Purkinje cells (PCs) dendritic arborization, loss of PCs and motor coordination, and muscle weakness with no effective treatment. We aim to develop a real‐time field‐programmable gate array (FPGA) prototype targeting the deep cerebellar nuclei (DCN) to close the loop for ataxia using conditional double knockout mice with deletion of PC‐specific LIM homeobox (Lhx)1 and Lhx5, resulting in abnormal dendritic arborization and motor deficits. Methods We implanted multielectrode array in the DCN and muscles of ataxia mice. The beneficial effect of open‐loop DCN‐DBS or closed‐loop DCN‐DBS was compared by motor behavioral assessments, electromyography (EMG), and neural activities (neurospike and electroencephalogram) in freely moving mice. FPGA board, which performed complex real‐time computation, was used for closed‐loop DCN‐DBS system. Results Closed‐loop DCN‐DBS was triggered only when symptomatic muscle EMG was detected in a real‐time manner, which restored motor activities, electroencephalogram activities and neurospike properties completely in ataxia mice. Closed‐loop DCN‐DBS was more effective than an open‐loop paradigm as it reduced the frequency of DBS. Conclusion Our real‐time FPGA‐based DCN‐DBS system could be a potential clinical strategy for alleviating cerebellar ataxia and other movement disorders. Conventional open‐loop DBS provides continuous stimulation, regardless of changes in physiologic state. Our FPGA‐based closed‐loop DBS system is triggered only when symptomatic muscle EEG is detected in a real‐time manner, which reduced the frequency and time of DBS, preventing over neural stimulation that shortens the battery life of stimulator. The real‐time FPGA‐based closed‐loop DBS system demonstrates a proof‐of‐concept, supporting its potential clinical application in integrating the new generation of implantable pulse generator and external wireless wearable EEG devices for movement disorder.

This book aims to propose the implementation and application of Fractional Order Systems (FOS). It is well known that FOS can be utilized in control applications and systems modeling, and their effectiveness has been proven in many theoretical works and simulation routines. A further and mandatory step for FOS real world utilization is their hardware implementation and applications on real systems modeling. With this viewpoint, introductory chapters are included on the definition of stability region of Fractional Order PID Controller and Chaotic FOS, followed by the practical implementation based on Microcontroller, Field Programmable Gate Array, Field Programmable Analog Array and Switched Capacitor. Another section is dedicated to FO modeling of Ionic Polymeric Metal Composite (IPMC). This new material will have applications in robotics, aerospace and biomedicine.

Molecular dynamics simulation is a common method to help humans understand the microscopic world. The traditional general‐purpose high‐performance computing platforms are hindered by low computational and power efficiency, constraining the practical application of large‐scale and long‐time many‐body molecular dynamics simulations. In order to address these problems, a novel molecular dynamics accelerator for the Tersoff potential is designed based on field‐programmable gate array (FPGA) platforms, which enables the acceleration of LAMMPS using FPGAs. Firstly, an on‐the‐fly method is proposed to build neighbor lists and reduce storage usage. Besides, multilevel parallelizations are implemented to enable the accelerator to be flexibly deployed on FPGAs of different scales and achieve good performance. Finally, mathematical models of the accelerator are built, and a method for using the models to determine the optimal‐performance parameters is proposed. Experimental results show that, when tested on the Xilinx Alveo U200, the proposed accelerator achieves a performance of 9.51 ns/day for the Tersoff simulation in a 55,296‐atom system, which is a 2.00×$$ \\times $$ increase in performance when compared to Intel I7‐8700K and 1.70×$$ \\times $$ to NVIDIA Tesla K40c under the same test case. In addition, in terms of computational efficiency and power efficiency, the proposed accelerator achieves improvements of 2.00×$$ \\times $$ and 7.19×$$ \\times $$ compared to Intel I7‐8700K, and 4.33×$$ \\times $$ and 2.11×$$ \\times $$ compared to NVIDIA Titan Xp, respectively. We propose an FPGA‐based molecular dynamics accelerator with customized computing architecture for the Tersoff potential. The designed accelerator achieves good acceleration of the Tersoff potential, showing the potential of extending LAMMPS to FPGAs for high power efficiency and high computational efficiency.

Power electronic converters are used for an efficient and controlled conversion of power generated from renewable energy sources and can interface generated power to the grid. Among available power converters, voltage source inverters (VSIs) have been widely employed for grid-connected applications due to better controllability with higher efficiency. Although various conventional, as well as modern control techniques, have been developed for grid connected VSI system, there is a need to select suitable control technique based on application and control requirements. Hardware-in-the-loop (HIL) is considered as a realistic approach for the development of system and control due to the inclusion of an actual hardware system. In this paper, a HIL approach is adopted for the comprehensive analysis and development of a grid connected VSI system using a field programmable gate array (FPGA). The control techniques must deal with trade-off, based on the features and limitations. Therefore, a grid-connected VSI system is developed considering employment of two different conventional control techniques: hysteresis current control (HCC) and PI-based space vector modulation (PI-SVM), as well as finite state model predictive control (FS-MPC) as a modern control technique for investigation considering different parameters. All three control systems are developed through a digital simulator of Xilinx that is integrated with MATLAB-Simulink, while considering an FPGA based system development and testing through FPGA HIL co-simulation methodology.

In order to expand the simulation scale of smart substation, a simulation model of the inlet-outlet line unit, as described by the 0/108 S conductance for multivalued coefficients pre-storage is presented in this paper. As a part of orders decomposition, the address conversion circuit for multivalued coefficients can reduce the computational burden of processing elements. For the convenience of the generalization of the real-time digital solver based on FPGA (FRTDS, FPGA: Field–Programmable Gate Array), the address conversion circuit for multivalued coefficients is matched with the guide word, the formation module of sampled value (SV) packet, and the resolution module of generic object oriented substation event (GOOSE) packet are associated with the application identification (APPID) in the Ethernet frame. The address conversion circuit for multivalued coefficients, the formation module of SV packet, and the resolution module of GOOSE packet are reconstructed via the orders. A hardware-in-the-loop real-time simulation platform for smart substation is built based on the novel FRTDS. A case is given to demonstrate the simulation calculating capability and the hardware-in-the-loop ability of the novel FRTDS.

FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a “learn by doing” approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

We present a fast and reconfigurable architecture for Shack–Hartmann wavefront sensing implemented on FPGA devices using a stream-based center of gravity to measure the spot displacements. By calculating the center of gravity around each incoming pixel with an optimal window matching the spot size, the common trade-off between noise and bias errors and dynamic range due to window size existing in conventional center of gravity methods is avoided. In addition, the accuracy of centroid estimation is not compromised when the spot moves to or even crosses the sub-aperture boundary, leading to an increased dynamic range. The calculation of the centroid begins while the pixel values are read from an image sensor and further computation such as slope and partial wavefront reconstruction follows immediately as the sub-aperture centroids are ready. The result is a real-time wavefront sensing system with very low latency and high measurement accuracy feasible for targeting on low-cost FPGA devices. This architecture provides a promising solution which can cope with multiple target objects and work in moderate scintillation.

This book uses a \"learn by doing\" approach to introduce the concepts and techniques of VHDL and FPGA to designers through a series of hands-on experiments. FPGA Prototyping by VHDL Examples provides a collection of clear, easy-to-follow templates for quick code development; a large number of practical examples to illustrate and reinforce the concepts and design techniques; realistic projects that can be implemented and tested on a Xilinx prototyping board; and a thorough exploration of the Xilinx PicoBlaze soft-core microcontroller.