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A new generation of aperture synthesis passive millimetre‐wave imager is being developed for security screening using 4096 element antennas with 3.5 GHz bandwidth, enabling high radiometric sensitivity at a video frame rate. This paper proposed a high performance digital correlator deployed in such system that uses integrated connectors to input a 1 GHz bandwidth, 32 I/Q input signals from IF processors. The proposed correlator is implemented up to 2080 of 2‐bit/4‐level (2B/4L) correlation units in a field programmable gate array (FPGA). A novel structure suitable for an FPGA is developed, occupying less than 11% of hardware resource utilisation, allowing a maximum clock frequency of over 289 MHz. A test system is built to verify the design, and a correlation efficiency above 99.4% is observed at the proposed interval, which outperforms other state‐of‐the‐art zero‐lag digital cross‐correlators. We introduce a novel 1 GHz 64‐channel digital correlator with 2B/4L quantisation circuit design based on field programmable gate array (FPGA). The overall design makes full use of hardware resources, aiming for high radiometric sensitivity through the integration of massive correlation units.

This second volume of an Artech House bestseller presents an enhanced approach toward product compliance and safety engineering. Written by experts in the field, this new volume presents practical material useful for novice and advanced practitioners. Safety aspects of product approvals, energy management, environmental concerns, material science, radiation, hazardous location, and global market access are explored. Practical features related to global market access are presented, including specific documentation and local labeling requirements, as well as language used for safety instructions and user manuals. Compliance and safety aspects of specific applications, such as information technology equipment, audio-video (multimedia), medical, household, alarms systems, luminaires (including LED-lamps) and lamp control, industrial machinery, and semiconductor manufacturing, are discussed. Environmental attributes, including temperature, atmospheric pressure, relative humidity, vibration, shock and packaging/transportation, and how they affect product safety, are analyzed. Information about testing (environmental, HALT, and HASS) is also provided, focusing on the compliance of electrical products with dedicated environmental regulation.

In principle, the recently proposed capacitive-coupling impedance spectroscopy (CIS) has the capability to acquire frequency spectra of complex electrical impedance sequentially on a millisecond timescale. Even when the measured object with time-varying unknown resistance Rx is capacitively coupled with the measurement electrodes with time-varying unknown capacitance Cx, CIS can be measured. As a proof of concept, this study aimed to develop a prototype that implemented the novel algorithm of CIS and circuit parameter estimation to verify whether the frequency spectra and circuit parameters could be obtained in milliseconds and whether time-varying impedance could be measured. This study proposes a dedicated processor that was implemented as field-programmable gate arrays to perform CIS, estimate Rx and Cx, and their digital-to-analog conversions at a certain time, and to repeat them continually. The proposed processor executed the entire sequence in the order of milliseconds. Combined with a front-end nonsinusoidal oscillator and interfacing circuits, the processor estimated the fixed Rx and fixed Cx with reasonable accuracy. Additionally, the combined system with the processor succeeded in detecting a quick optical response in the resistance of the cadmium sulfide (CdS) photocell connected in series with a capacitor, and in reading out their resistance and capacitance independently as voltages in real-time.

The JUNGFRAU 4‐megapixel (4M) charge‐integrating pixel‐array detector, when operated at a full 2 kHz frame rate, streams data at a rate of 17 GB s−1. To operate this detector for macromolecular crystallography beamlines, a data‐acquisition system called Jungfraujoch was developed. The system, running on a single server with field‐programmable gate arrays and general‐purpose graphics processing units, is capable of handling data produced by the JUNGFRAU 4M detector, including conversion of raw pixel readout to photon counts, compression and on‐the‐fly spot finding. It was also demonstrated that 30 GB s−1 can be handled in performance tests, indicating that the operation of even larger and faster detectors will be achievable in the future. The source code is available from a public repository. A new data acquisition and real‐time image analysis system with FPGAs and GPUs for kilohertz macromolecular crystallography applications is presented.

We present a data‐acquisition and ‐analysis framework for quasi‐elastic gamma‐ray scattering (QEGS) experiments at BL35XU of SPring‐8, equipped with an 840 kpixel CITIUS X‐ray detector operating at 17.4 kHz. The detector produces data at 27 GB s−1 (216 Gbps), and typical experiments involve acquisition over beam‐time periods longer than 24 h, generating datasets of 2.3 PB per day. To handle this volume, we constructed a data‐handling pipeline consisting of the detector, data reduction at the beamline and analysis tools at the data center. The data reduction employs field‐programmable gate array (FPGA)‐accelerated per‐pixel processing to reduce data entropy, followed by Zstandard compression on CPUs, achieving an average compression ratio of over 8000. The compressed data are transferred to the SPring‐8 data center within two to three minutes of data acquisition. At the data center, analysis tools are provided via the Open OnDemand platform, enabling incremental integration and spectral analysis through a web‐based interface without the need for high‐performance‐computing command‐line interaction. This data‐handling pipeline has been applied in QEGS user experiments, where it enabled timely feedback on experimental data, with integrated results available within six minutes and spectral analysis within seven minutes of integration. A high‐throughput field‐programmable gate array (FPGA)‐accelerated data‐reduction and ‐analysis pipeline combined with high‐performance computing enables the continuous handling of a 216 Gbps data stream from quasi‐elastic gamma‐ray scattering experiments at SPring‐8.

Aims The open‐loop nature of conventional deep brain stimulation (DBS) produces continuous and excessive stimulation to patients which contributes largely to increased prevalence of adverse side effects. Cerebellar ataxia is characterized by abnormal Purkinje cells (PCs) dendritic arborization, loss of PCs and motor coordination, and muscle weakness with no effective treatment. We aim to develop a real‐time field‐programmable gate array (FPGA) prototype targeting the deep cerebellar nuclei (DCN) to close the loop for ataxia using conditional double knockout mice with deletion of PC‐specific LIM homeobox (Lhx)1 and Lhx5, resulting in abnormal dendritic arborization and motor deficits. Methods We implanted multielectrode array in the DCN and muscles of ataxia mice. The beneficial effect of open‐loop DCN‐DBS or closed‐loop DCN‐DBS was compared by motor behavioral assessments, electromyography (EMG), and neural activities (neurospike and electroencephalogram) in freely moving mice. FPGA board, which performed complex real‐time computation, was used for closed‐loop DCN‐DBS system. Results Closed‐loop DCN‐DBS was triggered only when symptomatic muscle EMG was detected in a real‐time manner, which restored motor activities, electroencephalogram activities and neurospike properties completely in ataxia mice. Closed‐loop DCN‐DBS was more effective than an open‐loop paradigm as it reduced the frequency of DBS. Conclusion Our real‐time FPGA‐based DCN‐DBS system could be a potential clinical strategy for alleviating cerebellar ataxia and other movement disorders. Conventional open‐loop DBS provides continuous stimulation, regardless of changes in physiologic state. Our FPGA‐based closed‐loop DBS system is triggered only when symptomatic muscle EEG is detected in a real‐time manner, which reduced the frequency and time of DBS, preventing over neural stimulation that shortens the battery life of stimulator. The real‐time FPGA‐based closed‐loop DBS system demonstrates a proof‐of‐concept, supporting its potential clinical application in integrating the new generation of implantable pulse generator and external wireless wearable EEG devices for movement disorder.

This book aims to propose the implementation and application of Fractional Order Systems (FOS). It is well known that FOS can be utilized in control applications and systems modeling, and their effectiveness has been proven in many theoretical works and simulation routines. A further and mandatory step for FOS real world utilization is their hardware implementation and applications on real systems modeling. With this viewpoint, introductory chapters are included on the definition of stability region of Fractional Order PID Controller and Chaotic FOS, followed by the practical implementation based on Microcontroller, Field Programmable Gate Array, Field Programmable Analog Array and Switched Capacitor. Another section is dedicated to FO modeling of Ionic Polymeric Metal Composite (IPMC). This new material will have applications in robotics, aerospace and biomedicine.

Molecular dynamics simulation is a common method to help humans understand the microscopic world. The traditional general‐purpose high‐performance computing platforms are hindered by low computational and power efficiency, constraining the practical application of large‐scale and long‐time many‐body molecular dynamics simulations. In order to address these problems, a novel molecular dynamics accelerator for the Tersoff potential is designed based on field‐programmable gate array (FPGA) platforms, which enables the acceleration of LAMMPS using FPGAs. Firstly, an on‐the‐fly method is proposed to build neighbor lists and reduce storage usage. Besides, multilevel parallelizations are implemented to enable the accelerator to be flexibly deployed on FPGAs of different scales and achieve good performance. Finally, mathematical models of the accelerator are built, and a method for using the models to determine the optimal‐performance parameters is proposed. Experimental results show that, when tested on the Xilinx Alveo U200, the proposed accelerator achieves a performance of 9.51 ns/day for the Tersoff simulation in a 55,296‐atom system, which is a 2.00× $$ \\times $$increase in performance when compared to Intel I7‐8700K and 1.70× $$ \\times $$to NVIDIA Tesla K40c under the same test case. In addition, in terms of computational efficiency and power efficiency, the proposed accelerator achieves improvements of 2.00× $$ \\times $$and 7.19× $$ \\times $$compared to Intel I7‐8700K, and 4.33× $$ \\times $$and 2.11× $$ \\times $$compared to NVIDIA Titan Xp, respectively. We propose an FPGA‐based molecular dynamics accelerator with customized computing architecture for the Tersoff potential. The designed accelerator achieves good acceleration of the Tersoff potential, showing the potential of extending LAMMPS to FPGAs for high power efficiency and high computational efficiency.

Dr Donald Bailey starts with introductory material considering the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The design process for implementing an image processing algorithm on an FPGA is compared with that for a conventional software implementation, with the key differences highlighted. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage is given of a range of low and intermediate level image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques are illustrated with several example applications or case studies from projects or applications the author has been involved with. Issues such as interfacing between the FPGA and peripheral devices are covered briefly, as is designing the system in such a way that it can be more readily debugged and tuned. <ul type=\"disc\"> <li>Provides a bridge between algorithms and hardware</li> <li>Demonstrates how to avoid many of the potential pitfalls</li> <li>Offers practical recommendations and solutions</li> <li>Illustrates several real-world applications and case studies</li> <li>Allows those with software backgrounds to understand efficient hardware implementation</li> </ul> <p><i>Design for Embedded Image Processing on FPGAs</i>&#160;is ideal for researchers and engineers in the vision or image processing industry, who are looking at smart sensors, machine vision, and robotic vision, as well as FPGA developers and application engineers.</p> <p>The book can also be used by graduate students studying imaging systems, computer engineering, digital design, circuit design, or computer science. It can also be used as supplementary text for courses in advanced digital design, algorithm and hardware implementation, and digital signal processing and applications.</p> <p>Lecture slides for instructors available at:</p> <p>www.wiley.com/go/bailey/fpga</p>

Power electronic converters are used for an efficient and controlled conversion of power generated from renewable energy sources and can interface generated power to the grid. Among available power converters, voltage source inverters (VSIs) have been widely employed for grid-connected applications due to better controllability with higher efficiency. Although various conventional, as well as modern control techniques, have been developed for grid connected VSI system, there is a need to select suitable control technique based on application and control requirements. Hardware-in-the-loop (HIL) is considered as a realistic approach for the development of system and control due to the inclusion of an actual hardware system. In this paper, a HIL approach is adopted for the comprehensive analysis and development of a grid connected VSI system using a field programmable gate array (FPGA). The control techniques must deal with trade-off, based on the features and limitations. Therefore, a grid-connected VSI system is developed considering employment of two different conventional control techniques: hysteresis current control (HCC) and PI-based space vector modulation (PI-SVM), as well as finite state model predictive control (FS-MPC) as a modern control technique for investigation considering different parameters. All three control systems are developed through a digital simulator of Xilinx that is integrated with MATLAB-Simulink, while considering an FPGA based system development and testing through FPGA HIL co-simulation methodology.