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The frequency synthesizer performs a simple function of generating a desired frequency by manipulating a reference frequency signal, but stable and precise frequency generation is essential for reliable operation in mechanical equipment such as communication, control, surveillance, medical, and commercial fields. Frequency synthesis, which is commonly used in various contexts, has been used in analog and digital methods or hybrid methods. Especially in the field of communication, a precise frequency synthesizer is required for each frequency band, from very low-frequency AF (audio frequency) to high-frequency microwaves. The purpose of this paper is to design and implement a highly reliable frequency synthesizer for application to a railway track circuit systems using AF frequency only with the logic circuit of an FPGA (field programmable gate array) without using a microprocessor. Therefore, the development trend of analog, digital, and hybrid frequency synthesizers is examined, and a method for precise frequency synthesizer generation on the basis of the digital method is suggested. In this paper, the generated frequency generated by applying the digital frequency synthesizer using the ultra-precision algorithm completed by many trials and errors shows the performance of generating the target frequency with an accuracy of more than 99.999% and a resolution of mHz, which is much higher than the resolution of 5 Hz in the previous study. This highly precise AF-class frequency synthesizer contributes greatly to the safe operation and operation of braking and signaling systems when used in transportation equipment such as railways and subways.

5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not only optimized the chip dimensions, but also precludes the influence of process shrinks and has the advantage of noise immunity. The elements of novelties of this article are low phase noise and low power consumption. With 1.8 V supply voltage and locking at 5.22 GHz, measured results find that the output signal power is −8.03 dBm, the phase noise is −110.74 dBc/Hz at 1 MHz offset frequency and the power dissipation is 16.2 mW, while the die dimensions are 0.901 × 0.935 mm2.

A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.

Radio telescopes are among the applications with the highest demands on a local oscillator (LO), which is used to receive and process the signals coming from the sky. Therefore the modules providing the required LO signal have traditionally been big and complicated. To overcome this disadvantage, we implement our own integrated frequency synthesizer inside a small LO module in this article. With this synthesizer we are able to achieve a jitter of only 50 fs integrated from 10 Hz to 2.5 GHz offset at a carrier frequency of 75 GHz. This is in part achieved by a very low in-band phase noise of −111.8 dBc at 10 kHz offset. The stabilizable frequency range is 62–88 GHz. Thus achieving promising results to fulfill this very demanding task with integrated frequency synthesizers in the future.

Frequency-modulated continuous-wave radar systems profit from increasing the absolute bandwidths of the generated frequency chirps to improve range resolution. As the relative bandwidth of SiGe-voltage-controlled oscillators (VCOs) is limited to about 80%, increasing the center frequency fundamentally or via frequency multiplication is the most direct way to increase that absolute bandwidth. However, as some applications require penetration depth, which dramatically decreases with frequency, other solutions are necessary. Therefore, state-of-the-art concepts rely on the down-conversion of generated frequency chirps via two separately stabilized frequency sources. This article implements a novel architecture, offering relative bandwidths of >100% within a single phase-locked loop (PLL). Therefore, two VCOs at different center frequencies are fed into a down-conversion mixer, whose output is directly stabilized via that PLL with one loop filter generating both tuning voltages. Those circuit blocks can be summarized as one equivalent VCO, offering a higher relative bandwidth and a significantly more linear tuning curve. Thereby, a solution to limited relative bandwidths with high VCO gain variation of single VCO synthesizers is offered while substantially reducing the hardware and implementation effort compared to the state-of-the-art.

The architecture of a pulse-continuous model of a multi-detector pulse-phase locked loop system of a frequency synthesizer with frequency dividers with a fractional-variable division coefficient for determining the level of fractional interference is presented. Analytical expressions were obtained and a program was developed in the MATLAB system to determine the level of fractional interference when using a frequency synthesizer of a multiaccumulator. The results of spectral analysis of the output signal phase of a frequency synthesizer in a broadband sampled phase-locked loop system are presented. A method is proposed for determining the level of fractional interference in a frequency synthesizer, taking into account the time quantization of processes in an ideal pulse element using the mathematical model of a frequency synthesizer in the state space. The effect of the spread of the response delays of multiple pulse-phase detectors from the multiaccumulator on the level of fractional interference is analyzed. The results of a spectral analysis of the level of fractional interference using the mathematical model of a frequency synthesizer that takes into account the delay in the operation of a separate pulse-phase detector are presented.

The current work employs the HMC830 phase-locked loop chip to design a frequency synthesizer operating in the L-band. The frequency synthesizer can provide a local oscillation signal for the RF receiver front end. This article employs the phase-locked synthesis technique to describe the design scheme. Due to the advantages of the passive loop filters, such as simplicity, low cost, and low phase noise, a passive fourth-order RLC loop filter is proposed to improve the output signal quality and reduce phase noise. The performance of this loop filter is compared with the passive fourth-order RC loop filter. The effects of these two loop filters on phase noise, loop capture time, and spur suppression are analyzed. Subsequently, the design scheme, simulation analysis, and test results of the frequency synthesizer are presented under these two loop filters. The test results indicate that the passive fourth-order RLC loop filter outperforms the passive fourth-order RC loop filter; its output signal phase noise is higher than −100 dBc/Hz@1 kHz, loop capture time is less than 100 us, and spur suppression is better than 60 dBc. This frequency synthesizer can provide high-performance local oscillation signals for wireless communication equipment such as transmitters and receivers. It meets the application requirements of many radio communication circuit structures and has good application prospects.

This book remains the standard text on the subject by providing complete and up-to-date coverage of both practical and theoretical aspects of modern frequency synthesizers and their components. Featuring contributions from leading experts in the field, this classic volume describes loop fundamentals, noise and spurious responses, special loops, loop components, multiloop synthesizers, and more. Practical synthesizer examples illustrate the design of a high-performance hybrid synthesizer and performance measurement techniques - offering readers clear instruction on the various design steps and design rules. The second edition includes extensively revised content throughout, including a modern approach to dealing with the noise and spurious response of loops and updated material on digital signal processing and architectures. Reflecting today's technology, new practical and validated examples cover a combination of analog and digital synthesizers and hybrid systems. Enhanced and expanded chapters discuss implementations of direct digital synthesis (DDS) architectures, the voltage-controlled oscillator (VCO), crystal and other high-Q based oscillators, arbitrary waveform generation, vector signal generation, and other current tools and techniques.

A novel delay cell circuit for differential ring oscillator (DRO) with large tuning range along with application in charge pump phase lock loop (CP-PLL) frequency synthesizer has been presented in this paper. Using 0.18μm CMOS technology with power supply of 1.8 V, the two DRO architectures: 3-stage and 5-stage, were built and simulated. In both 3-stage and 5-stage DROs, single controlled voltage is employed. The suggested 3-stage and 5-stage DRO circuits generate a tuning range of 96.77 MHz-5.296 GHz and 36.33 MHz-2.803 GHz, respectively. The % total harmonic distortion (%THD) of both DRO architectures is also evaluated. The suggested 3-stage and 5-stage DROs consume 6.63 mW and 11.05 mW power at an oscillation frequency of 4.76 GHz and 2.479 GHz, respectively. At an offset frequency of 10 MHz from the oscillation frequency, the proposed circuits have phase noise of -119.93 dBc/Hz and -128.24 dBc/Hz, respectively. The layout of proposed design has been drawn and pre- and post-layout simulation results show satisfactory variations of tuning range and phase noise of proposed design. The suggested circuit’s robustness is verified with the help of PVT and Monte Carlo analysis. When compared to contemporary research, the proposed DROs have the widest tuning range. Proposed DRO application in CP-PLL frequency synthesizer has locking time of 1.17 μs and shows good settling behaviour with dynamic parameter variations.

A clock-induced-spurs detector, composed of a programmable low-pass filter (LPF), energy detector and spur detection algorithm, is presented and applied to a four-channel 1 gigabit-samples-per-second (GSPS) direct digital frequency synthesizer (DDS). The proposed detector realizes the detection of spurs based on energy-detection, and the spur detection algorithm is adopted to automatically extract the amplitude and phase of clock-induced spurs, generated by the intermodulation of harmonic spurs and multiple clocks. Finally, the extracted features are sent to auxiliary DDS to decrease the target spur, following which the detector can be turned off to save power. Additionally, the detected characteristics under different output conditions can be read out through the interface for rapid frequency switching. The proposed detector integrated into a DDS is fabricated with a 65 nm complementary metal oxide semiconductor (CMOS) process and has an area of 190 μm × 320 μm. The measured power consumption is roughly 38 mW, consuming 6% that of a single-channel DDS. The test results show that the spurious-free dynamic range (SFDR) of this DDS can be successfully enhanced from −43.1 dBc to roughly −59.9 dBc without any off-chip instruments. This effectively proves that the detection accuracy of this detector can reach around −81 dBm.