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Series-winding topology (SWT) could improve the DC-link voltage utilization, as open-winding topology does. Meanwhile, it can greatly reduce the number of power devices. Firstly, for the half-bridge power modules (HBPMs)-based inverter, an N-phase series-winding motor only requires N + 1 HBPMs for driving. On the other hand, such SWT also brings new challenges to the drive system. A zero-sequence loop is introduced into the motor windings due to SWT. The generated zero-sequence current would degrade the total harmonic distortion of the phase currents and produce the additional torque ripple. Moreover, current sensors are typically integrated with the HBPMs. However, in SWT, their measured results are the leg currents of the inverter, not the phase currents of the motor, which is crucial to the motor control. Thus, this paper mainly focuses on the aforementioned problems in a three-phase series-winding permanent-magnet synchronous motor (TPSW-PMSM) drive with HBPM-based inverter. Firstly, to control the zero-sequence subspace, the voltage vector distribution of TPSW-PMSM is analyzed. In addition, two voltage vectors with zero-sequence components are selected to generate the zero-sequence voltage. Then, the phase currents are reconstructed according to the leg currents from the current sensors on HBPMs. Based on the above, the deadbeat predictive current control (DBPCC) scheme is proposed for a TPSW-PMSM drive with HBPM-based inverter. It provides the TPSW-PMSM drive with fast dynamic response and effective zero-sequence current suppression. Finally, both simulation and experimental results verify the feasibility and effectiveness of the proposed DBPCC scheme.

Silicon carbide (SiC) half-bridge power modules are widely utilized in new energy power generation, electric vehicles, and industrial power supplies. To address the research gap in collaborative validation between electro-thermal coupling models and process reliability, this paper proposes a closed-loop methodology of “design-simulation-process-validation”. This approach integrates in-depth electro-thermal simulation (LTspice XVII/COMSOL Multiphysics 6.3) with micro/nano-packaging processes (sintering/bonding). Firstly, a multifunctional double-pulse test board was designed for the dynamic characterization of SiC devices. LTspice simulations revealed the switching characteristics under an 800 V operating condition. Subsequently, a thermal simulation model was constructed in COMSOL to quantify the module junction temperature gradient (25 °C → 80 °C). Key process parameters affecting reliability were then quantified, including conductive adhesive sintering (S820-F680, 39.3 W/m·K), high-temperature baking at 175 °C, and aluminum wire bonding (15 mil wire diameter and 500 mW ultrasonic power/500 g bonding force). Finally, a double-pulse dynamic test platform was established to capture switching transient characteristics. Experimental results demonstrated the following: (1) The packaged module successfully passed the 800 V high-voltage validation. Measured drain current (4.62 A) exhibited an error of <0.65% compared to the simulated value (4.65 A). (2) The simulated junction temperature (80 °C) was significantly below the safety threshold (175 °C). (3) Microscopic examination using a Leica IVesta 3 microscope (55× magnification) confirmed the absence of voids at the sintering and bonding interfaces. (4) Frequency-dependent dynamic characterization revealed a 6 nH parasitic inductance via Ansys Q3D 2025 R1 simulation, with experimental validation at 8.3 nH through double-pulse testing. Thermal evaluations up to 200 kHz indicated 109 °C peak temperature (below 175 °C datasheet limit) and low switching losses. This work provides a critical process benchmark for the micro/nano-manufacturing of high-density SiC modules.

Power conversion equipment based on high-voltage SiC devices offers significant advantages in efficiency and power density. However, during high-voltage, high-power switching operations, severe electromagnetic interference (EMI) can easily occur. It could cause the false triggering of devices and result in converter failure in severe conditions. This paper firstly establishes a mathematical model and conducts simulation analysis of the conducted common-mode interference path in high-voltage SiC device gate driver circuits. Based on the driver circuit architecture, a modeling method for the common-mode interference conduction network in half-bridge submodules is proposed, clarifying the key factors contributing to high common-mode currents. A low common-mode current design methodology for high-voltage SiC submodules is presented, including driver loop structure optimization, capacitor design, and submodule integration. A highly integrated 3.3 kV SiC-based submodule prototype has been successfully developed, serving as a building block for constructing multilevel modular converters (MMCs). Simulation and experimental results indicate that the amplitude of the common-mode current is primarily influenced by the coupling capacitance of the auxiliary power supply, exhibiting a proportional relationship. The developed SiC submodule achieves high-speed switching at 50 kV/μs under a 2 kV DC bus voltage, with excellent thermal stability and low common-mode current characteristics, validating the effectiveness of the proposed model and design approach.

In the photovoltaic industry, there is great interest in increasing the power output of solar cells to achieve grid parity and to promote the widespread use of solar cells. However, despite many developments, a phenomenon called light-induced degradation causes the efficiency of solar cells to deteriorate over time. This study proposes a treatment that can be applied to cells within solar modules. It uses a half-bridge resonance circuit to induce a magnetic field and selectively heat Al electrodes in the solar cells. The electrical state of a solar module was measured in real time as it was being heated, and the results were combined with a kinetics simulation using a cyclic reaction. As the temperature of the solar module increased, the time taken to reach the saturation point and the recovery time decreased. Moreover, the value of the saturation point increased. The light-induced degradation activation energy was similar to results in the existing literature, suggesting that the kinetic model was valid and applicable even when 72 cells were connected in series. This demonstrates that an entire solar module can be treated when the cells are connected in series, and in future multiple modules, could be connected in series during treatment.

The light-induced degradation (LID) phenomenon in solar cells reduces power generation output. Previously, a method was developed to prevent LID where a group III impurity that can replace boron is added to the silicon wafer. However, in a subsequent study, performance degradation was observed in gallium-doped solar wafers and cells, and a degradation pattern similar to that occurring in light and elevated temperature-induced degradation (LeTID) was reported. In this study, a 72-cell module was fabricated using gallium-doped PERC cells, and the treatment of the LID process for carrier injection in the range of 1 to 7 A at 130 °C was analyzed using kinetic theory. We selectively heated only the solar cells inside a 72-cell module using a half-bridge resonance circuit for remote heating. To monitor the treatment of LID process in real time, a custom multimeter manufactured using an ACS758 current sensor and a microcomputer was used. Least-squares curve fitting was performed on the measured data using a reaction kinetics model. When the carrier-injection condition was applied to the gallium-doped PERC solar cell module at a temperature of 130 °C, the observed degradation and treatment pattern were similar to LeTID. We assumed that the treatment rate would increase as the size of the injected carrier increased; however, the 5 A condition exhibited the fastest treatment rate. It was deduced that the major factors of change in the overall treatment of the LID process vary depending on the rate of conversion from the LID state to the treatment state. In conclusion, it can be expected that the deterioration state of the gallium-doped solar cell module changes due to the treatment rate that varies depending on the carrier-injection conditions.

This article proposes an electrothermal averaged model of a half-bridge DC–DC converter containing a power module. This kind of model enables the computation of characteristics of DC–DC converters using DC analysis. The form of the elaborated model is presented. Both the electrical and thermal properties of the analyzed DC–DC converter are included in this model. This is the first averaged electrothermal model of a DC–DC converter which makes it possible to compute the junction temperature of all the semiconductor devices and magnetic components. The accuracy of the model was experimentally verified in a wide range of switching frequencies and output currents. Particularly, the influence of mutual thermal couplings between the transistors contained in the considered module on the characteristics of the converter and the junction temperature of the transistors is analyzed.

This paper analyses the implementation of modular multi level converter (MMLC) in the application of grid connected Photovoltaic system in an efficient manner. As MMLC exhibits properties of high modularity and scalability, it is highly suitable for the high power applications, which makes MMLC to be preferred in this study as an apt replacement of the conventional DC–DC converters. A unified control using a cascaded fuzzy logic controller (CFLC) is proposed for both the maximum power point tracking and modular 7 level converter (M7LC) control. The CFLC is analogized with the conventional PI and Fuzzy controllers under both the normal and partial shaded conditions. The entire system is assessed with the aid of using MATLAB simulation. The observed outcomes exhibit that total harmonic distortion (THD) of line current is minimum under all operating conditions when the CFLC is used for M7LC. The prototype of the proposed M7LC with CFLC is implemented in FPGA SPARTAN 6E controller for the experimental validation. The proposed approach delivers lesser THD of  1.02 % under normal condition and  1.12 % under partial shading condition.

This study presents a theoretical analysis of half- and full-bridge modular multi-level converters for HVDC transmission applications. The constraints and the degrees of freedom in the choice of switching functions, and the harmonic content of the sum and difference of arm voltages and currents, are highlighted by the analysis. The authors prove that under balanced switching conditions, dc and even harmonic components are absent from the difference variables and odd harmonics are absent from the sum variables, whereas the pole voltages are free from harmonics. Using an energy function approach, it is shown that the sorting strategy for module voltage balancing is stable and practically independent of the dynamics of the rest of the system. The module voltages settle down to a band around the average value because of the finite switching frequency, for which an upper bound is provided.

A novel zero-voltage switching (ZVS) DC/DC converter with series connected transformers for high input voltage application is presented. Two series half-bridge legs and two split capacitors are adopted in order to limit the voltage stress of active switches at Vin/2. Two resonant converter modules are used to reduce current stress on active switches and rectifier diodes. Based on the series resonant tank, the active switches are turned on at ZVS and rectifier diodes are turned off at zero-current switching. Thus, the switching loss of active switches and reverse recovery problem of rectifier diodes are reduced. The secondary windings are connected in series to ensure that the primary winding currents are balanced. Finally, experiments are provided to verify the effectiveness of the proposed converter.