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In the wake of COP26 and the growing urgency of addressing climate change, achieving carbon neutrality by 2050 has become a central global objective. This imperative extends to industries like computer hardware manufacturing, which are now actively pursuing decarbonization strategies through the strategic adoption of renewable energy sources and energy efficiency enhancements. This research paper assessed the CO2 emission mitigation potential of a hybrid system of photovoltaic (PV) roof and cogeneration where a large factory of computer hardware manufacturing in tropical Thailand was selected as a study site. On one hand, a one-Megawatt photovoltaic system was installed over the roof of the production building to generate electricity from solar radiation to serve the building. On the other hand, a twenty-four-Megawatt cogeneration system of gas engines as the prime mover was used to supply power to meet the building’s electricity demand. Waste heat from the gas engine was used by the absorption chiller to generate chilled water for cooling inside the building. Based on the system equipment specifications, the annual simulation using Thailand’s solar radiation showed that the installed photovoltaic system could generate electricity of 1,412.4 MWhelec/year while the implementation of the absorption chillers for cooling helped to reduce the electrical energy consumed by the traditional electric chiller by 10,211.4 MWhelec/year. In our study case where the CO2 emission of the grid power was 0.4758 kgCO2/kWhelec in the year 2022 and was reduced to 0.350 kgCO2/kWhelec in the year 2050, the total CO2 emission mitigation from the hybrid photovoltaic and cogeneration system with the genset efficiency of 50% and the waste heat recovery of 60% could reduce approximately 207,388.5TonCO2 for over 20 years as compared to the scenario where the grid electricity alone powered the building. These findings underscored the critical role of the proposed hybrid system in addressing the climate crisis and exemplified how the industry could make meaningful strides toward more environmental sustainability.

Digital integrated circuits play an important role in the development of new information technologies and support Industry 4.0 from a hardware point of view. There is great pressure on electronics companies to reduce the time-to-market for product development as much as possible. The most time-consuming stage in hardware development is functional verification. As a result, many industry and academic stakeholders are investing in automating this crucial step in electronics production. The present work aims to automate the functional verification process by means of genetic algorithms that are used for generating the relevant input stimuli for full simulation of digital design behavior. Two important aspects are pursued throughout the current work: the implementation of genetic algorithms must be time-worthy compared to the application of the classical constrained-driven generation and the verification process must be implemented using tools accessible to a wide range of practitioners. It is demonstrated that for complex designs, functional verification powered by the use of genetic algorithms can go beyond the classical method of performing verification, which is based on constrained-random stimulus generation. The currently proposed methods were able to generate several sets of highly performing stimuli compared to the constraint-random stimulus generation method, in a ratio ranging from 57:1 to 205:1. The performance of the proposed approaches is comparable to that of the well-known NSGA-II and SPEA2 algorithms.

Software comes from India, hardware comes from China. Why is that? Why did China and India take such different paths to global dominance in new high-tech industries? Will their paths continue to diverge or converge? How can other countries learn from their successes – and failures – in reaching global scale in new industries? To answer these questions, this book presents the first rigorous comparison of the growth of the IT industries in China and India, based on interviews with over 300 companies. It explains the different growth paths of the software and hardware sectors in each country, providing insights into the factors behind the emergence of China and India as global economic powers. It provides a compelling case study of how differences in economic policies and the investment climate affect industrial growth. This book sheds new light on common debates on 'China versus India', on why India is the software capital of the world while China is a manufacturing powerhouse. It refutes common myths about the growth of these industries – for example, the role of Non-Resident Indians or the Y2K problem in the growth of the Indian software industry, the role of government intervention in industrial growth, and the relative size of China and India's software industries.

Distributed digital manufacturing of free and open-source scientific hardware (FOSH) used for scientific experiments has been shown to in general reduce the costs of scientific hardware by 90–99%. In part due to these cost savings, the manufacturing of scientific equipment is beginning to move away from a central paradigm of purchasing proprietary equipment to one in which scientists themselves download open-source designs, fabricate components with digital manufacturing technology, and then assemble the equipment themselves. This trend introduces a need for new formal design procedures that designers can follow when targeting this scientific audience. This study provides five steps in the procedure, encompassing six design principles for the development of free and open-source hardware for scientific applications. A case study is provided for an open-source slide dryer that can be easily fabricated for under $20, which is more than 300 times less than some commercial alternatives. The bespoke design is parametric and easily adjusted for many applications. By designing using open-source principles and the proposed procedures, the outcome will be customizable, under control of the researcher, less expensive than commercial options, more maintainable, and will have many applications that benefit the user since the design documentation is open and freely accessible.

The number of nodes typically used in sensory networks is growing rapidly, leading to large amounts of redundant data being exchanged between sensory terminals and computing units. To efficiently process such large amounts of data, and decrease power consumption, it is necessary to develop approaches to computing that operate close to or inside sensory networks, and that can reduce the redundant data movement between sensing and processing units. Here we examine the concept of near-sensor and in-sensor computing in which computation tasks are moved partly to the sensory terminals. We classify functions into low-level and high-level processing, and discuss the implementation of near-sensor and in-sensor computing for different physical sensing systems. We also analyse the existing challenges in the field and provide possible solutions for the hardware implementation of integrated sensing and processing units using advanced manufacturing technologies. This Perspective examines the concept of near-senor and in-sensor computing in which computation tasks are moved partly to the sensory terminals, exploring the challenges facing the field and providing possible solutions for the hardware implementation of integrated sensing and processing units using advanced manufacturing technologies.

With the proliferation of ultrahigh-speed mobile networks and internet-connected devices, along with the rise of artificial intelligence (AI) 1 , the world is generating exponentially increasing amounts of data that need to be processed in a fast and efficient way. Highly parallelized, fast and scalable hardware is therefore becoming progressively more important 2 . Here we demonstrate a computationally specific integrated photonic hardware accelerator (tensor core) that is capable of operating at speeds of trillions of multiply-accumulate operations per second (10 12 MAC operations per second or tera-MACs per second). The tensor core can be considered as the optical analogue of an application-specific integrated circuit (ASIC). It achieves parallelized photonic in-memory computing using phase-change-material memory arrays and photonic chip-based optical frequency combs (soliton microcombs 3 ). The computation is reduced to measuring the optical transmission of reconfigurable and non-resonant passive components and can operate at a bandwidth exceeding 14 gigahertz, limited only by the speed of the modulators and photodetectors. Given recent advances in hybrid integration of soliton microcombs at microwave line rates 3 – 5 , ultralow-loss silicon nitride waveguides 6 , 7 , and high-speed on-chip detectors and modulators, our approach provides a path towards full complementary metal–oxide–semiconductor (CMOS) wafer-scale integration of the photonic tensor core. Although we focus on convolutional processing, more generally our results indicate the potential of integrated photonics for parallel, fast, and efficient computational hardware in data-heavy AI applications such as autonomous driving, live video processing, and next-generation cloud computing services. An integrated photonic processor, based on phase-change-material memory arrays and chip-based optical frequency combs, which can operate at speeds of trillions of multiply-accumulate (MAC) operations per second, is demonstrated.

Physical Unclonable Functions (PUFs) address the inherent limitations of conventional hardware security solutions in edge-computing devices. Despite impressive demonstrations with silicon circuits and crossbars of oxide memristors, realizing efficient roots of trust for resource-constrained hardware remains a significant challenge. Hybrid organic electronic materials with a rich reservoir of exotic switching physics offer an attractive, inexpensive alternative to design efficient cryptographic hardware, but have not been investigated till date. Here, we report a breakthrough security primitive exploiting the switching physics of one dimensional halide perovskite memristors as excellent sources of entropy for secure key generation and device authentication. Measurements of a prototypical 1 kb propyl pyridinium lead iodide (PrPyr[PbI 3 ]) weak memristor PUF with a differential write-back strategy reveals near ideal uniformity, uniqueness and reliability without additional area and power overheads. Cycle-to-cycle write variability enables reconfigurability, while in-memory computing empowers a strong recurrent PUF construction to thwart machine learning attacks. Despite the impressive demonstrations with silicon and oxide memristors, realizing efficient roots of trust for resource-constrained hardware remains a challenge. Here, the authors exploit switching behavior in one dimensional perovskite memristors to design security primitives for key generation and device authentication.

Diverse and wide-range applications of integrated circuits (ICs) and the development of Cyber Physical System (CPS), more and more third-party manufacturers are involved in the manufacturing of ICs. Unfortunately, like software, hardware can also be subjected to malicious attacks. Untrusted outsourced manufacturing tools and intellectual property (IP) cores may bring enormous risks from highly integrated. Attributed to this manufacturing model, the malicious circuits (known as Hardware Trojans, HTs) can be implanted during the most designing and manufacturing stages of the ICs, causing a change of functionality, leakage of information, even a denial of services (DoS), and so on. In this paper, a survey of HTs is presented, which shows the threatens of chips, and the state-of-the-art preventing and detecting techniques. Starting from the introduction of HT structures, the recent researches in the academic community about HTs is compiled and comprehensive classification of HTs is proposed. The state-of-the-art HT protection techniques with their advantages and disadvantages are further analyzed. Finally, the development trends in hardware security are highlighted.

Digital three-dimensional (3D) scanning is a cutting-edge metrology method that can digitally reconstruct surface topography with high precision and accuracy. Such metrology can help traditional manufacturing processes evolve into a smart manufacturing paradigm, which can ensure product quality by automated sensing and control. However, due to limitations with the spatial resolution, scanning speed, and size of the focusing area, commercially available systems cannot be directly used for in-process monitoring in smart manufacturing. For example, a metal 3D printer requires a scanner with second-level sensing, micron-level spatial resolution, and a centimeter-scale scanning region. Among the 3D scanning technologies, structured light 3D scanning can meet the scanning speed criteria but not the spatial resolution and scanning region criteria. This work addresses these challenges by reducing the field of view of a structured light scanner system while increasing the image sensor pixel resolution. Improvements to spatial resolution and accuracy are achieved by establishing hardware selection criteria, integrating the proper hardware, designing a scale-appropriate calibration target, and developing noise reduction procedures during calibration. An additively manufactured Ti-6Al-4V part was used to validate the effectiveness of the proposed 3D scanner. The scanning result shows that both melt pool geometry and overall shape can be clearly captured. In the end, the scanning accuracies of the proposed scanner and a professional-grade commercial scanner are validated with a nanometer-level accuracy white light interferometer using high-density point cloud data. Compared to the commercial scanner, the proposed scanner improves the spatial resolution from 48 to 5 μm and the accuracy from 108.5 to 0.5 μm. Compared to the white light interferometer, the proposed scanner improves the scanning and processing speed from 2 to 20 s.

The discovery of ferroelectricity in oxides that are compatible with modern semiconductor manufacturing processes, such as hafnium oxide, has led to a re-emergence of the ferroelectric field-effect transistor in advanced microelectronics. A ferroelectric field-effect transistor combines a ferroelectric material with a semiconductor in a transistor structure. In doing so, it merges logic and memory functionalities at the single-device level, delivering some of the most pressing hardware-level demands for emerging computing paradigms. Here, we examine the potential of the ferroelectric field-effect transistor technologies in current embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models. We highlight the material- and device-level challenges involved in high-volume manufacturing in advanced technology nodes (≤10 nm), which are reminiscent of those encountered in the early days of high- K -metal-gate transistor development. We argue that the ferroelectric field-effect transistors can be a key hardware component in the future of computing, providing a new approach to electronics that we term ferroelectronics. This Perspective examines the use of ferroelectric field-effect transistor technologies in current embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models, arguing that the devices will be a key component in the development of data-centric computing.