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Property-driven hardware verification provides a promising way to uncover design vulnerabilities. However, developing security properties that check for highly concealed security vulnerabilities remains a significant challenge. In this paper, we propose a scheme, called HT-PGFV, to implement hardware Trojan security property assertion automatic generation and formal security verification for Trojan-infected designs. In our scheme, we develop a hardware Trojan security property assertion generation method for automated hardware which can extract hardware Trojan security properties from Trojan-infected designs by performing the three main steps of Trojan-infected signal identification based on feature matching, influence-cone-analysis-based Trojan path identification, and information flow trace mining, and formulate them as SystemVerilog assertions. In addition, we develop a formal security verification method based on information flow analysis which can formally verify hardware Trojan security properties and detect hardware Trojans violating information flow security policies by checking the security of information flows via our developed RT-level hardware information flow security models. The proposed method is demonstrated on several Trojan benchmarks from Trust-Hub. Experimental results show that our scheme can generate hardware Trojan security property assertions for Trojan-infected designs and detect information leakage and functionality change hardware Trojans activated by external inputs or internal conditions.

Intellectual property (IP) security has emerged as a critical concern in semiconductor industries. In the domain of hardware IP security, logic locking is a commonly used technique to prevent unauthorized access to IPs. This article proposes a conceptual pipeline to enhance the hardware IP security by leveraging generative models and logic locking concepts (GAN4IP) for hardware IP security. The proposed approach uses the concept of logic locking and generative adversarial networks (GANs) in a unified fashion to design secure hardware IPs. The GAN architecture uses deep learning techniques and graph-based representations of digital circuits to build obfuscated designs that can predict the behavior of locked netlists and generate secure designs. The proposed perspective method opens up new avenues for further investigation of highly secure electronic system design and has the potential to significantly impact the field of hardware IP security.

Side-channel attacks are attacks against cryptographic devices that are based on information obtained by leakage into cryptographic algorithm hardware implementation rather than algorithm implementation. Power attacks are based on analyzing the power consumption of a corresponding input and obtaining access to this method. The power profile of the encryption circuit maintains an interaction with the input to be processed, allowing the attacker to guess the hidden secrets. In this work, we presented a novel architecture of masked logic cells that are resistant to power attacks and have reduced cell numbers. The presented masking cell reduces the relationship between the actual power and the mathematically approximated power model measured by the Pearson correlation coefficient. The security aspect of the logic cell is measured with the correlation coefficient of the person. The proposed mask-XOR and mask-AND cells are 0.0053 and 0.3respectively, much lower than the standard XOR and AND cells of 0.134 and 0.372respectively.

This study reviews the current situation regarding design protection in the microelectronics industry. Over the past 10 years, the designers of integrated circuits (IC) and intellectual properties (IP) have faced increasing threats including counterfeiting, reverse-engineering and theft. This is now a critical issue for the microelectronics industry, mainly for fabless designers and IP designers. Coupled with increasing pressure to decrease the cost and increase the performance of ICs, the design of a secure, efficient, lightweight protection scheme for design data is a serious challenge for the hardware security community. However, several published works propose different ways to protect design data including functional locking, hardware obfuscation and IC/IP identification. This study presents a survey of academic research on the protection of design data. It concludes with the need to design an efficient protection scheme based on several properties.

Physical unclonable function (PUF) has emerged as a promising and important security primitive for use in modern systems and devices, due to their increasingly embedded, distributed, unsupervised, and physically exposed nature. However, optical PUFs based on speckle patterns, chaos, or ‘strong’ disorder are so far notoriously sensitive to probing and/or environmental variations. Here we report an optical PUF designed for robustness against fluctuations in optical angular/spatial alignment, polarization, and temperature. This is achieved using an integrated quasicrystal interferometer (QCI) which sensitively probes disorder while: (1) ensuring all modes are engineered to exhibit approximately the same confinement factor in the predominant thermo-optic medium (e. g. silicon), and (2) constraining the transverse spatial-mode and polarization degrees of freedom. This demonstration unveils a new means for amplifying and harnessing the effects of ‘weak’ disorder in photonics and is an important and enabling step toward new generations of optics-enabled hardware and information security devices.

In order to realize image information security starting from the data source, challenge–response (CR) device authentication, based on a Physically Unclonable Function (PUF) with a 2 Mpixel CMOS image sensor (CIS), is studied, in which variation of the transistor in the pixel array is utilized. As each CR pair can be used only once to make the CIS PUF resistant to the modeling attack, CR authentication with CIS can be carried out 4050 times, with basic post-processing to generate the PUF ID. If a larger number of authentications is required, advanced post-processing using Lehmer encoding can be utilized to carry out authentication 14,858 times. According to the PUF performance evaluation, the authentication error rate is less than 0.001 ppm. Furthermore, the area overhead of the CIS chip for the basic and advanced post-processing is only 1% and 2%, respectively, based on a Verilog HDL model circuit design.

The Internet-of-Things (IoT) has gained significant importance in all aspects of daily life, and there are many areas of application for it. Despite the rate of expansion and the development of infrastructure, such systems also bring new concerns and challenges. Security and privacy are at the top of the list and must be carefully considered by designers and manufacturers. Not only do the devices need to be protected against software and network-based attacks, but proper attention must also be paid to recently emerging hardware-based attacks. However, low-cost unit software developers are not always sufficiently aware of existing vulnerabilities due to these kinds of attacks. To tackle the issue, various platforms are proposed to enable rapid and easy evaluation against physical attacks. Fault attacks are the noticeable type of physical attacks, in which the normal and secure behavior of the targeted devices is liable to be jeopardized. Indeed, such attacks can cause serious malfunctions in the underlying applications. Various studies have been conducted in other research works related to the different aspects of fault injection. Two of the primary means of fault attacks are clock and voltage fault injection. These attacks can be performed with a moderate level of knowledge, utilizing low-cost facilities to target IoT systems. In this paper, we explore the main parameters of the clock and voltage fault generators. This can help hardware security specialists to develop an open-source platform and to evaluate their design against such attacks. The principal concepts of both methods are studied for this purpose. Thereafter, we conclude our paper with the need for such an evaluation platform in the design and production cycle of embedded systems and IoT devices.

With the advancement of the Internet of Things (IoTs) technology, security issues have received an increasing amount of attention. Since IoT devices are typically resource-limited, conventional security solutions, such as classical cryptography, are no longer applicable. A physically unclonable function (PUF) is a hardware-based, low-cost alternative solution to provide security for IoT devices. It utilizes the inherent nature of hardware to generate a random and unpredictable fingerprint to uniquely identify an IoT device. However, despite existing PUFs having exhibited a good performance, they are not suitable for effective application on resource-constrained IoT devices due to the limited number of challenge-response pairs (CRPs) generated per unit area and the large hardware resources overhead. To solve these problems, this article presents an ultra-lightweight reconfigurable PUF solution, which is named RPPUF. Our method is built on pico-PUF (PPUF). By incorporating configurable logics, one single RPPUF can be instantiated into multiple samples through configurable information K. We implement and verify our design on the Xilinx Spartan-6 field programmable gate array (FPGA) microboards. The experimental results demonstrate that, compared to previous work, our method increases the uniqueness, reliability and uniformity by up to 4.13%, 16.98% and 10.5%, respectively, while dramatically reducing the hardware resource overhead by 98.16% when a 128-bit PUF response is generated. Moreover, the bit per cost (BPC) metric of our proposed RPPUF increased by up to 28.5 and 53.37 times than that of PPUF and the improved butterfly PUF, respectively. This confirms that the proposed RPPUF is ultra-lightweight with a good performance, making it more appropriate and efficient to apply in FPGA-based IoT devices with constrained resources.

Attacks on Internet of Things (IoT) devices are on the rise. Physical Unclonable Functions (PUFs) are proposed as a robust and lightweight solution to secure IoT devices. The main advantage of a PUF compared to the current classical cryptographic solutions is its compatibility with IoT devices with limited computational resources. In this paper, we investigate the maturity of this technology and the challenges toward PUF utilization in IoT that still need to be addressed.

Hardware Trojans (HTs) are an emerging threat for integrated circuits integrity and their applications. Trying to find efficient HT detection methods is necessary. However, before detecting them, HTs need to be created with an efficient method and their effects need to be understood. There are very few studies which describe HTs implementation methods and the methods used are not convenient for systematic study of HTs effects. The Trust-Hub website, known for hardware security in general, had published a full HT implementation tutorial, which is not completely satisfying. This study proposes a stealthy and reusable HT implementation method on field programmable gate arrays at the layout level adapted for the study of different HTs with the same non-infected circuit. Created for a systematic study of the effects brought by different HTs, the proposed approach allows designers to insert stealthy HTs inside the same circuit in order to create different realistic infected circuits. HTs implementation results on an advance encryption standard system and detection experiments based on side-channel are also presented in this study. The implementation method the authors propose can be used with scripts in order to accelerate the insertions of HTs variants.