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Memristive logic device is a promising unit for beyond von Neumann computing systems and 2D materials are widely used because of their controllable interfacial properties. Most of these 2D memristive devices, however, are made from semiconducting chalcogenides which fail to gate the off‐state current. To this end, a crossbar device using 2D HfSe2 is fabricated, and then the top layers are oxidized into “high‐k” dielectric HfSexOy via oxygen plasma treatment, so that the cell resistance can be remarkably increased. This two‐terminal Ti/HfSexOy/HfSe2/Au device exhibits excellent forming‐free resistive switching performance with high switching speed (<50 ns), low operation voltage (<3 V), large switching window (103), and good data retention. Most importantly, the operation current and the power consumption reach 100 pA and 0.1 fJ to 0.1 pJ, much lower than other HfO based memristors. A functionally complete low‐power Boolean logic is experimentally demonstrated using the memristive device, allowing it in the application of energy‐efficient in‐memory computing. An energy‐efficient memristive device based on 2D HfSe2 oxides is fabricated, which is able to implement functionally complete Boolean logic with operation current down to 100 pA. The low‐power switching is realized by the formation and rupture of cone‐shaped O‐vacancy filaments in the ultrathin Hf−Se−O layer.

With the recently increasing prevalence of deep learning, both academia and industry exhibit substantial interest in neuromorphic computing, which mimics the functional and structural features of the human brain. To realize neuromorphic computing, an energy‐efficient and reliable artificial synapse must be developed. In this study, the synaptic ferroelectric field‐effect‐transistor (FeFET) array is fabricated as a component of a neuromorphic convolutional neural network. Beyond the single transistor level, the long‐term potentiation and depression of synaptic weights are achieved at the array level, and a successful program‐inhibiting operation is demonstrated in the synaptic array, achieving a learning accuracy of 79.84% on the Canadian Institute for Advanced Research (CIFAR)‐10 dataset. Furthermore, an efficient self‐curing method is proposed to improve the endurance of the FeFET array by tenfold, utilizing the punch‐through current inherent to the device. Low‐frequency noise spectroscopy is employed to quantitatively evaluate the curing efficiency of the proposed self‐curing method. The results of this study provide a method to fabricate and operate reliable synaptic FeFET arrays, thereby paving the way for further development of ferroelectric‐based neuromorphic computing. The primary challenge that ferroelectric field‐effect transistors face is their vulnerability to the repeated program/erase cycle. To solve this issue, an efficient self‐curing method is presented. The proposed method successfully recovers synaptic fatigue damage, enhancing learning accuracy in the convolutional neural network.

This review delves into the advancements in optoelectronic logic gate (OELG) devices, emphasizing their transformative potential in computational technology through the integration of optical and electronic components. OELGs present significant advantages over traditional electronic logic gates, including enhanced processing speed, bandwidth, and energy efficiency. The evolution of OELG architectures from single‐device, single‐logic systems to more sophisticated multidevice, multilogic, and reconfigurable OELGs is comprehensively explored. Key advancements include the development of materials and device structures enabling multifunctional logic operations and the incorporation of in‐memory functionalities, critical for applications in high‐performance computing and real‐time data processing. This review also addresses the challenges that need to be overcome, such as stability, durability, integration with existing semiconductor technologies, and efficiency. By summarizing current research and proposing future directions, this review aims to guide the ongoing development of next‐generation optoelectronic architectures, poised to redefine the landscape of optical computing, communication, and data processing. This review delves into advancements in optoelectronic logic gate (OELG) devices, emphasizing their transformative potential in computational technology through the integration of optical and electronic components. It highlights the evolution from single‐device, single‐logic systems to multidevice, multilogic, and in‐memory OELGs, driven by the need to enhance speed, bandwidth, and energy efficiency.

Analog storage through synaptic weights using conductance in resistive neuromorphic systems and devices inevitably generates harmful heat dissipation. This thermal issue not only limits the energy efficiency but also hampers the very‐large‐scale and highly complicated hardware integration as in the human brain. Here we demonstrate that the synaptic weights can be simulated by reconfigurable non‐volatile capacitances of a ferroelectric‐based memcapacitor with ultralow‐power consumption. The as‐designed metal/ferroelectric/metal/insulator/semiconductor memcapacitor shows distinct 3‐bit capacitance states controlled by the ferroelectric domain dynamics. These robust memcapacitive states exhibit uniform maintenance of more than 104 s and well endurance of 109 cycles. In a wired memcapacitor crossbar network hardware, analog vector‐matrix multiplication is successfully implemented to classify 9‐pixel images by collecting the sum of displacement currents (I = C × dV/dt) in each column, which intrinsically consumes zero energy in memcapacitors themselves. Our work sheds light on an ultralow‐power neural hardware based on ferroelectric memcapacitors. We demonstrate a robust memcapacitor by stacking ferroelectric capacitor on the metal‐insulator‐semiconductor structure. It possesses a long retention time of more than 104 s and well endurance of 109 cycles. Ultralow‐power in‐memory computing based on ferroelectric memcapacitor array intrinsically consumes zero energy in memcapacitors themselves. It sheds light on an ultralow‐power neural hardware based on ferroelectric memcapacitors.

Security is a critical challenge in the integrated circuit (IC) industry, yet device‐level hardware security remains largely underexplored. Most existing solutions necessitate modifications to current technology nodes and typically address only a single security threat, leaving them vulnerable to diverse attacks while incurring substantial costs in area, energy, and resources. In this study, an out‐of‐the‐box security solution is proposed that integrates an in‐memory sensing and computing (IMSC) architecture based on α‐In2Se3 transistor, specifically designed for versatile and multimodal secure applications. By leveraging the unique ferroelectric, optoelectronic, and semiconducting properties of α‐In2Se3, the study demonstrates the secure transistor's electronic and optoelectronic synaptic behaviors, along with its capability for reconfigurable logic operations. Based on these, the secure transistor successfully implements four key security primitives: anticounterfeiting, watermarking, logic locking, and IC camouflaging in a single‐transistor structure, offering robust protection against counterfeit ICs, intellectual property theft, and reverse engineering. The multimodal secure transistor demonstrates the functional flexibility in addressing various security threats. A multimodal secure transistor‐integrated in‐memory sensing and computing architecture is demonstrated by leveraging its electronic and optoelectronic synaptic behaviors. Key security primitives, such as anticounterfeiting, watermarking, logic locking, and camouflaging, are implemented within a compact single‐transistor structure, providing a scalable and resource‐efficient solution to address hardware security threats in the era of the Internet of Things.

Memristors offer a promising solution to address the performance and energy challenges faced by conventional von Neumann computer systems. Yet, stochastic ion migration in conductive filament often leads to an undesired performance tradeoff between memory window, retention, and endurance. Herein, a robust memristor based on oxygen‐rich SnO2 nanoflowers switching medium, enabled by seed‐mediated wet chemistry, to overcome the ion migration issue for enhanced analog in‐memory computing is reported. Notably, the interplay between the oxygen vacancy (Vo) and Ag ions (Ag+) in the Ag/SnO2/p++‐Si memristor can efficiently modulate the formation and abruption of conductive filaments, thereby resulting in a high on/off ratio (>106), long memory retention (10‐year extrapolation), and low switching variability (SV = 6.85%). Multiple synaptic functions, such as paired‐pulse facilitation, long‐term potentiation/depression, and spike‐time dependent plasticity, are demonstrated. Finally, facilitated by the symmetric analog weight updating and multiple conductance states, a high image recognition accuracy of ≥ 91.39% is achieved, substantiating its feasibility for analog in‐memory computing. This study highlights the significance of synergistically modulating conductive filaments in optimizing performance trade‐offs, balancing memory window, retention, and endurance, which demonstrates techniques for regulating ion migration, rendering them a promising approach for enabling cutting‐edge neuromorphic applications. This study leverages the synergy of modulating conductive filament to render a significant breakthrough in memory window, extending up to 1 million, and retention for up to 10 years, fostering advanced paradigms in bionics. These results underscore the judicious regulation of ion migration as a viable route to high‐performance memristors for neuromorphic computing applications.

The rapid development of deep learning enables significant breakthroughs for intelligent edge‐terminal devices. However, neural network training for edge computing is currently overly dependent on cloud service platforms, resulting in low adaptivity for fast‐changing real‐world environments. The training energy efficiency is also strictly constrained by the traditional Von‐Neumann architecture with separate memory and processing units. To improve the adaptability and energy efficiency of edge‐terminal devices, a fully parallel online neural network training scheme based on electrochemical random‐access memory (ECRAM) arrays is proposed and validated. By exploiting the intrinsic linearity and nonlinearity functionalities of ECRAMs brought by varying numbers and amplitudes of programming pulses, a physical implementation of in situ multiplication using pulse‐based training is achieved, realizing fully parallel in situ computation and storage of outer product between two vectors. It can not only greatly accelerate the computation of weight gradients in neural network training but also significantly reduce the time complexity, latency, and energy overheads associated with data handling compared to traditional hardware implementations for this task. The ECRAM‐based online training system reduces the energy overhead of the training process by 30× when compared to the same training process executed on traditional computing hardware. By leveraging the intrinsic functionalities of electrochemical random‐access memory, the conductance response to pulse amplitude and quantity enables stochastic multiplication and parallel outer‐product operations between two vectors. This approach significantly accelerates weight gradient computations while reducing time complexity, latency, and energy overheads related to data management, enhancing the computing efficiency of online training in edge‐terminal devices to a new paradigm.

In the big data era, sensing multi‐modal information in memory is highly demanded for the sake of artificial intelligence applications to overcome the limitations of the von Neumann architecture. Different from traditional sensing methodologies, mechanoluminescence (ML) materials, which emit light in response to mechanical force without any external power supply, present intriguing prospects for technological developments. However, most of the ML materials only demonstrate instantaneous luminescence, severely hampering the exploitation of ML in sophisticated applications where non‐volatile control is indispensable. Herein, a non‐volatile, multilevel mechano‐optical memory system is proposed, based on a crafted combination of a self‐recoverable ML material, ZnS:Cu, and a photostimulated luminescence (PSL) phosphor Ca0.25Sr0.75S:Eu (CaSrS:Eu). By integrating ML with PSL effect, a robust six‐level non‐volatile memory is achieved, in which the multilevel memory states allow for computational capability without electrical interference. Specifically, the reliable multilevel and non‐volatile response enables Boolean logic operations. Furthermore, neuromorphic visual pattern pre‐processing is implemented, resulting in a substantial increase in recognition accuracy from 20% to 80%. These findings endow force‐responsive phosphors with memory capability, fully leveraging the capabilities of ML and offering a new strategy for developing mechano‐optical hardware and concepts for future intelligent applications. The integration of photostimulated luminescence with self‐recoverable mechanoluminescence materials endows the system with the capability to record and visually interpret mechanical information, concurrently exhibiting a six‐level non‐volatile memory architecture. This configuration showcases superior multi‐level and non‐volatile responses, which serve as the foundation for in‐memory computing. Moreover, the system demonstrates its efficacy in performing Boolean logic operations and neuromorphic pattern pre‐processing.

A memristive stateful neural network allowing complete Boolean in‐memory computing attracts high interest in future electronics. Various Boolean logic gates and functions demonstrated so far confirm their practical potential as an emerging computing device. However, spatio‐temporal efficiency of the stateful logic is still too limited to replace conventional computing technologies. This study proposes a ternary‐state memristor device (simply a ternary memristor) for application to ternary stateful logic. The ternary‐state implementable memristor device is developed with bilayered tantalum oxide by precisely controlling the oxygen content in each oxide layer. The device can operate 157 ternary logic gates in one operational clock, which allows an experimental demonstration of a functionally complete three‐valued Łukasiewicz logic system. An optimized logic cascading strategy with possible ternary gates is ≈20% more efficient than conventional binary stateful logic, suggesting it can be beneficial for higher performance in‐memory computing. A ternary state memristor is reported that exhibits two abrupt switching functions, by stacking two layers of tantalum oxide. Ternary logic gates including a functionally complete system and a ternary full adder are experimentally demonstrated using stateful neural networks, which is complete in‐memory computing. The ternary full adder is proven to be more efficient than the binary one.

Analog in‐memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on‐chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal‐oxide semiconductor (Si‐CMOS) and capacitor‐based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si‐CMOS leakage currents, resulting in a deterioration of training accuracy. Here, a novel 6T1C synaptic device using only n‐type indium gaIlium zinc oxide thin film transistor (IGZO TFT) with low leakage current and a capacitor is proposed, allowing not only linear and symmetric weight update but also sufficient retention time and parallel on‐chip training operations. In addition, an efficient and realistic training algorithm to compensate for any remaining device non‐idealities such as drifting references and long‐term retention loss is proposed, demonstrating the importance of device‐algorithm co‐optimization. A novel 6T1C synaptic device based on indium gallium zinc oxide thin film transistor (IGZO TFT) and capacitor and a novel optimized training algorithm, retention‐centric Tiki‐Taka algorithm, is proposed. Through a new training scheme by co‐optimizing the device and algorithm, modified national institute of standards and technology (MNIST) on‐chip training accuracy of over ≈97% even in wide retention requirements is obtained.