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Reformer reduces redundant self‐attention computations via hash bucketing. In this study, we introduce a SRAM‐based digital‐analogue hybrid reformer computing‐in‐memory (ReCIM) accelerator macro. This macro presents an absolute maximum value addressing circuit which facilitates the hash bucketing process and enables the utilisation of strongly‐correlated (S‐C) vectors for attention mechanism computations, thereby improving computational efficiency and saving memory space. Additionally, we introduce a reusable weight array which is suitable for matrix operations across various processes of self‐attention, minimising unnecessary area overhead and enhancing device reusability. The proposed 4 Kb ReCIM macro was analysed using 28‐nm CMOS technology. Simulation results demonstrate that the macro achieves a frequency of 500 MHz at a supply voltage of 0.9 V. During the hash bucketing process, energy efficiency reaches 9.74 TOPS/W. In this study, we introduce a SRAM‐based digital‐analogue hybrid reformer computing‐in‐memory accelerator macro. This macro presents an absolute maximum value addressing circuit which facilitates the hash bucketing process and enables the utilisation of strongly‐correlated (S‐C) vectors for attention mechanism computations, thereby improving computational efficiency and saving memory space. Simulation results show that the data processing frequency for implementing hash bucketing is as high as 500 MHz, and the energy efficiency is 9.74 TOPS/W.

This paper presents a wide‐range, fast‐lock duty‐cycle corrector (DCC) with a 5‐bit successive‐approximation register (SAR). An inverter‐based bang‐bang duty‐cycle detector (BBDCD) is equalised before each comparison to suppress hysteresis, enabling deterministic decisions and a fixed 4‐cycle per‐bit schedule. The duty‐cycle adjuster (DCA) uses a controller frequency code for range adjustment and applies delay equalisation to limit code‐dependent delay during updates. A half‐LSB post‐bias then halves the SAR quantisation‐error bound without extra cycles. Post‐layout simulations in 28‐nm CMOS show operation from 0.8 to 3.2 GHz over 38%–62% input duty with a 20‐cycle lock, ≤1.0% maximum duty error, and 1.73 mW at 3.2 GHz. This letter presents a wide‐range, fast‐lock DCC for NAND Flash interfaces using an inverter‐based equalised BBDCD and 5‐bit SAR control. A half‐LSB post‐bias halves the quantisation‐error bound while maintaining ≤1% duty error and 1.73 mW power at 3.2 GHz in 28‐nm CMOS.

This work proposes a 6T1R non‐volatile SRAM (nvSRAM) cell based on resistive memory (RRAM) with a small area overhead and low store power compared to previous designs. It features (1) reusing the transistors in the SRAM cell for accessing the RRAM cell, (2) a voltage‐division (VD)‐based restore process with reduced DC current and (3) a trimmable multi‐cycle (TMC) store process to reduce data backup and recovery errors. We fabricated a 1 kb VD‐6T1R nvSRAM test array with back‐end‐of‐line integrated metal oxide RRAM cells in a 180 nm CMOS process. The reuse of transistors allows the VD‐6T1R cell structure to occupy only 1.14× the area of a standard 6T SRAM cell. The store and restore operations were experimentally verified at the array level. The restore error rates of the fabricated test array can be effectively suppressed using TMC store cycles. The restore errors in the fabricated 1 kb cell array can be eliminated after five cycles. This work proposes a 6T1R non‐volatile SRAM (nvSRAM) cell based on resistive memory (RRAM) with a small area overhead and low store power compared to previous designs. It features (1) reusing the transistors in the SRAM cell for accessing the RRAM cell, (2) a voltage‐division (VD)‐based restore process with reduced DC current and (3) a trimmable multi‐cycle store process to reduce data backup and recovery errors. A 1 kb VD‐6T1R nvSRAM test array is demonstrated using 180 nm CMOS process.

A 4‐tap time‐domain decision feedback equalizer (TD‐DFE) is presented to implement a multi‐tap DFE in a matched DQ (data)‐DQS (strobe) tree architecture. Traditionally, matched architecture holds an advantage in terms of power noise immunity, but it suffers from low‐speed performance due to the unavailability of decision feedback equalizer (DFE) applications. By adopting the proposed TD‐DFE, both high‐speed operation and power noise immunity can be achieved within the matched architecture. An 8‐DQ parallel receiver with the proposed 4‐tap TD‐DFE, designed in 28 nm CMOS, achieves a data rate of 20 Gb/s with 0.6 UI eye‐opening even with 215 mV power fluctuations. This adjusts pulse width to cancel inter‐symbol interference (ISI) through combination of serial and loop‐unrolled pulse width modulation units. Furthermore, it offers immunity to power supply induced jitter (PSIJ) thanks to advantage of DQ‐DQS delay matching. The proposed scheme can promise to resolve the traditional performance limitation of the DQ‐DQS matched tree type over a data rate of tens Gb/s.

This work proposes a storage element (SE) design for in‐memory computing (IMC). Using the proposed SE design, an IMC array has been constructed to enable in‐situ updates of stored weights. Compared with some existing related works which employ 2n bit cells for storing an n‐bit value, the proposed structure in this work exhibits a O(n) complexity of area overhead, which means that only n bit cells are needed to store n‐bit values, offering a significant improvement in silicon area usage. Compared to the purely digitally‐controlled weight update schemes, the approach proposed in this work demonstrates an approximate 1.47× increase in power consumption. Furthermore, it exhibits superior robustness compared to existing work. Additionally, the proposed SE design can achieve the necessary shift functionality in the cutting‐edge floating‐point (FP)‐IMC architecture through simple control mechanisms. This work proposes a storage element (SE) design for in‐memory computing (IMC). Using the proposed SE design, an IMC array has been constructed to enable in‐situ updates of stored weights. Additionally, the proposed SE design can achieve the necessary shift functionality in the cutting‐edge floating‐point IMC architecture through simple control mechanisms.

The increasing demand for electronics in harsh environment applications has inspired investigation of silicon carbide (SiC)-based devices and circuits, due to its superior electrical properties. Several researchers have demonstrated the viability of 4H-SiC control circuitry by developing small scale logic circuits entirely in 4H-SiC. However, development and design of memory elements, which is a critical component in any electronic system, is still not fully explored. To bridge this gap, this paper presents, a complete bipolar, static random access memory (SRAM) column that includes the memory cell and the peripheral circuitry, designed to exploit the unique properties of SiC. Simulation results for the proposed memory show stable operation across a wide range of temperatures (27 °C – 500 °C) with good noise margins and access speeds while running at a supply voltage as low as 5 V. This work validates the potential of developing memory architectures in 4H-SiC, paving the way for realizing small-sized digital systems for harsh environments.

An error-correcting code (ECC) immune to bit errors can make memory performance severely degraded since incomplete-word ECC write requests lead to inefficient operations on a dual in-line memory module (DIMM). A DIMM controller efficient for such ECC operations is proposed. The key idea is that read-to-write and write-to-read operations caused by incomplete-word ECC write requests are split into independent read and write operations, and then the read and write operations are individually scheduled under data coherence constraints. Experimental results show that the proposed DIMM controller achieves 11% shorter memory latency, and 9.3% higher memory utilisation, on average, than the latest conventional DIMM controller in industrial multimedia applications. Moreover, it achieves up to 2.1 times higher memory performance on synthetic benchmarks.

A computer built entirely using transistors based on carbon nanotubes, which is capable of multitasking and emulating instructions from the MIPS instruction set, is enabled by methods that overcome inherent challenges with this new technology. Computing with carbon nanotube transistors Carbon nanotubes have long been touted as promising building blocks for computers based on carbon rather than silicon. A main motivation towards this goal is the potential for circuits using carbon nanotube transistors to achieve high energy efficiency. Various carbon nanotube electronic circuit blocks have been demonstrated previously, but Max Shulaker et al . now reach a true milestone in the fields of carbon electronics and nanoelectronics by building a simple but functional computer made entirely from carbon nanotube transistors. Composed of 178 transistors, each containing between 10 and 200 carbon nanotubes, it runs a simple operating system and is capable of multitasking: it performs four tasks (summarized as instruction fetch, data fetch, arithmetic operation and write-back) and can run two different programs concurrently. The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies 1 , 2 . Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems 3 , 4 .

An antifuse structure that is fully compatible with the standard floating-gate technology is presented. The antifuse consists of an oxide-nitride-oxide dielectric layer, sandwiched between polysilicon and N-well layers. The characteristics of the antifuse are investigated. The off-state resistance of the antifuse is larger than 10 GΩ. The programmed antifuses show linear ohmic characteristics and have a tight resistance distribution centred around 350 Ω. The time dependent dielectric breakdown measurements show that the extrapolated lifetime of the unprogrammed antifuse at 5.5 V is as long as 40 years, and the resistance change of post-program antifuses under the continuous reading mode test is lower than 5%.

Recent developments in the controlled movement of domain walls in magnetic nanowires by short pulses of spin-polarized current give promise of a nonvolatile memory device with the high performance and reliability of conventional solid-state memory but at the low cost of conventional magnetic disk drive storage. The racetrack memory described in this review comprises an array of magnetic nanowires arranged horizontally or vertically on a silicon chip. Individual spintronic reading and writing nanodevices are used to modify or read a train of ~10 to 100 domain walls, which store a series of data bits in each nanowire. This racetrack memory is an example of the move toward innately three-dimensional microelectronic devices.