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High-efficiency video coding (HEVC) is the next generation standard of video coding. The deblocking filter (DF) constitutes a significant part of the HEVC decoder complexity. A three-step parallel framework (TPF) is proposed for the H.264/AVC DF, which is also suitable for HEVC except the third step. The third step of the TPF is replaced with a directed acyclic graph-based order. Experiments show that the proposed method dramatically accelerates more than the state-of-the-art parallel method.

Preserving the visual quality is a major constraint for any algorithm in image and video processing applications. AVC and HEVC are the extensively used video coding standards for various video processing applications in recent days. These coding standards use filters to preserve the visual quality of the processed video. To retain the quality of the reconstructed video, AVC uses an in-loop filter, called the deblocking filter, while HEVC uses two in-loop filters, the sampling adaptive offset filter and the deblocking filter. These filters are implemented in hardware by adopting various optimization techniques such as reduction of power utilization, reduction of algorithm complexity, and consuming lesser area. The quality of the reconstructed video should not be impacted by these optimization measures. For the HEVC/H.265 coding standard, a parallel edge deblocking filter architecture is designed, and the effectiveness of the parallel edge filter architecture is evaluated using various quantization values for various resolutions. The quality of the parallel edge filter architecture is on par with the HEVC reference model.

In-loop filtering significantly helps detect and remove blocking artifacts across block boundaries in low bitrate coded High Efficiency Video Coding (HEVC) frames and improves its subjective visual quality in multimedia services over communication networks. However, on faster processing of the complex videos at a low bitrate, some visible artifacts considerably degrade the picture quality. In this paper, we proposed a four-step fuzzy based adaptive deblocking filter selection technique. The proposed method removes the quantization noise, blocking artifacts and corner outliers efficiently for HEVC coded videos even at low bit-rate. We have considered Y (luma), U (chroma-blue), and V (chroma-red) components parallelly. Finally, we have developed a fuzzy system to detect blocking artifacts and use adaptive filters as per requirement in all four quadrants, namely up 45°, down 45°, up 135°, and down 135° across horizontal and vertical block boundaries. In this context, experimentation is done on a wide variety of videos. An objective and subjective analysis is carried out with MATLAB software and Human Visual System (HVS). The proposed method substantially outperforms existing post-processing deblocking techniques in terms of YPSNR and BD_rate. In the proposed method, we achieved 0.32–0.97 dB values of YPSNR. Our method achieved a BD_rate of +1.69% for the luma component, −0.18% (U) and −1.99% (V) for chroma components, respectively, with respect to the state-of-the-art methods. The proposed method proves to have low computational complexity and has better parallel processing, hence suitable for a real-time system in the near future.

This paper describes efficient hardware architecture for the deblocking filter used in H.264/AVC baseline profile video coding standard. The deblocking filter is a computationally and data intensive tool leading to an increased execution time of both encoding and decoding processes. In fact, we propose a novel edge filter ordering which needs 64 clock cycles to filter a Macroblock (MB). A specified memory organization is also applied in order to avoid unnecessarily waiting for availability of the pixels that will be filtered. The proposed architecture includes both pipelining and parallel processing techniques and is implemented in synthesizable HDL. This hardware is designed to be used as module of a complete H.264/AVC decoder which the functionality was validated on Nios II at 100 MHz.

This paper proposes a parallelization method for a deblocking filter in a high-efficiency video coding (HEVC) decoder based on complexity estimation. A deblocking filter of HEVC is generally considered to be appropriate for data-level parallelism (DLP) because there are no data-level dependencies among adjacent blocks in the horizontal and vertical filtering processes. However, an imbalanced workload can increase the idle time on some of the threads, and thus, the maximum parallel performance cannot be achieved with only DLP. To alleviate this problem, the proposed method estimates the computational complexity by utilizing the coding unit (CU) segment information and the on/off flag of the deblocking filter in advance. Then, the workload is distributed equally across all threads. The experimental results indicate that the proposed method can accelerate the decoding speed by a factor of 3.97, with six threads on top of the sequential deblocking filtering. In addition, the ratio of the maximum elapsed time to ideal elapsed time is reduced to approximately 21 %, as compared to conventional DLP-based parallel deblocking filtering methods that do not implement a complexity estimation method.

Deblocking filter is one of the most time consuming modules in the H.264/AVC decoder as indicated in many studies. Therefore, accelerating deblocking filter is critical for improving the overall decoding performance. This paper proposes a novel parallel algorithm for H.264/AVC deblocking filter to speed the H.264/AVC decoder up. We exploit pixel-level data parallelism among filtering steps, and observe that results of each filtering step only affect a limited region of pixels. We call this “the limited propagation effect”. Based on this observation, the proposed algorithm could partition a frame into multiple independent rectangles with arbitrary granularity. The proposed parallel deblocking filter algorithm requires very little synchronization overhead, and provides good scalability. Experimental results show that applying the proposed parallelization method to a SIMD optimized sequential deblocking filter achieves up to 95.31% and 224.07% speedup on a two-core and four-core processor, respectively. We have also observed a significant speedup for H.264/AVC decoding, 21% and 34% on a two-core and four-core processor, respectively.