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This letter proposes a ring‐VCO‐based integer‐N phase‐locked loop (PLL) with a wide frequency output range and fast frequency transitions for multi‐standard applications. To reduce power consumption, two key techniques are introduced. First, a VCO gain calibration unit calibrates the variable resistor‐based V‐to‐I converter, ensuring a consistent frequency tuning slop under process, voltage and temperature (PVT) variations. Second, a pulse‐swallow divider and timing control unit suppress unnecessary frequency fluctuation and achieve fast phase locking. This design enables PLL to reach the target frequency with 500 ns even under PVT variations. The proposed PLL covers 850 MHz to 3.3 GHz, achieving −107.3 dBc/Hz phase noise at a 10 MHz offset, with 6 mW power consumption at 3.3 GHz and an active area of 0.09 mm2. This work presents a ring‐VCO‐based integer‐N phase‐locked loop (PLL) with a wide frequency range (850 MHz–3.3 GHz) and fast frequency transitions. A VCO gain calibration unit and a pulse‐swallow divider with timing control enhance stability and power efficiency, achieving 500 ns locking time under process, voltage and temperature variations. The PLL achieves −107.3 dBc/Hz phase noise at a 10 MHz offset with 6 mW power consumption in a 0.09 mm2 area.

This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and for eliminating the delta–sigma modulator (DSM) noise inherent in conventional fractional-N designs. However, this advantage is countered by the critical need to calibrate the gain of the TDC. The previously proposed dual-interpolated TDC(DI-TDC) was proposed as a solution to this problem, but strong spurs were still generated due to the TDC resolution, which easily became non-uniform due to PVT variation, degrading performance. To overcome these problems, this work proposes a DPLL with a new calibration system that ensures consistent TDC resolution matching the period of the digitally controlled oscillator (DCO) and operating in both the foreground and background, thereby maintaining consistent performance despite PVT variations. This study proposes a DPLL using a calibrated dual-interpolated TDC that effectively compensates for PVT variations and improves the stability and performance of the DPLL. The PLL was fabricated in a 28-nm CMOS process with an active area of only 0.019 mm2, achieving an integrated phase noise (IPN) performance of −17.5 dBc, integrated from 10 kHz to 10 MHz at a PLL output of 570 MHz and −20.5 dBc at 1.1 GHz. This PLL operates within an output frequency range of 475 MHz to 1.1 GHz. Under typical operating conditions, it consumes only 930 µW with a 1.0 V supply.

Time-domain all-digital-phase-locked-loop phase-shift-keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low-voltage nanoscale CMOS techology. Data-bit extraction as well as phase control for loop locking can be effectively achieved in a time domain with simple logic operators such as positive-edge-trigger RESET/SET (pRSFF) and delay flip flops (DFF). Pulse width of the phase-control signal is sampled and passed on to the digitally-controlled oscillator (DCO) for frequency and phase adjustment. Two different phase control methods have been employed to appropriately alter a duty cycle of the phase-control signal. The first option is performed by multiplexing a single-phase DCO signal as selected by the extracted data bits. The second technique uses m DCO phases simultaneously for phase-control detection with the incoming m-PSK signal. This helps reduce the intertwined loop of the first method to a single-loop structure. This modular BPSK, QPSK, and 8PSK demodulation concept has been successfully verified by measurement with discrete components at a carrier frequency of 100 kHz operating under a 5-V supply.

Existing studies on commutation failure during fault recovery (CFFR) in line-commutated converter high-voltage direct current (LCC-HVDC) systems often neglect the critical influence of phase-locked loop phase tracking error (PLL-PTE) and fail to provide effective control strategies to address this issue. This paper investigates the influence of PLL-PTE on CFFR through electromagnetic transient simulations based on a modified CIGRE benchmark model. The study reveals that phase angle jump (PAJ) caused by DC power fluctuations (DPF) and AC network reconfigurations (ANR) is the fundamental source of PLL-PTE, which in turn leads to the occurrence of CFFR. To mitigate this, a novel control strategy is proposed that dynamically adjusts the extinction angle based on historical and predicted PAJ data. Simulation results demonstrate that the proposed method effectively suppresses CFFR under various fault conditions, including different fault types, locations, resistances, and initiation times. Compared with existing control schemes, the proposed approach avoids adverse side effects while exhibiting strong robustness and adaptability. The proposed control strategy significantly enhances the stability and reliability of LCC-HVDC systems, offering great potential for practical application in increasingly complex power grid environments.

In renewable power generation systems, ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters. Nowadays, the phase-locked loop (PLL) technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions. Even though a lot of PLLs have been proposed, an overview and comparative analysis of multiple PLLs can be helpful for practical applications. In addition, the weak grid condition is a great challenge for the system. Therefore, this study first presents an overview of the existing PLLs together with their general structures and basic working principles. Depending on the implementation of the phase detector, the PLL can be divided into three categories: power-based PLL (pPLL), orthogonal-signal-generator-based PLL (OSG-PLL) and adaptive-filter-based PLL (AF-PLL). Then, from the above classification, seven typical single-phase PLLs are selected for further study. Finally, some test results are given, and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.

In this paper, a customizable low-cost voltage waveform generator based on a real-time desktop PC and embedded data acquisition card synchronized with Coordinated Universal Time (UTC) is presented. A software approach to phase-locked loop synchronization with an external Global Positioning System (GPS) pulse signal is utilized to achieve a time uncertainty of ±1μs. This avoids expensive hardware modules for synchronization and timing purposes, which are commonly presented in literature. Besides the application for controlling the test platform, our own phasor data concentrator (PDC) application is running concurrently on the host PC. The latter is used for collecting and comparing the syncrophasor data from the test platform against the syncrophasor data measured by phasor measurement units (PMUs) under the test. The paper describes all procedures for generating reference test signals. Numerous case studies were performed, and experimental results for steady-state compliance as well as frequency ramp and phase modulation tests for dynamic compliance are presented in detail. All tests confirm that customizable test platform meets the requirements of IEEE/IEC standards. Compared to other calibrators, the cost as well as the specifications and point-by-point concept of data processing makes the described test platform suitable for performance analysis of PMU algorithms implemented on various development boards.

An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for space application at 3.2 GHz is presented here. Most clock recovery circuits need a very low phase noise and jitter performance and are thus based on LC-type oscillators. These excellent performances come at the expense of a very poor integration density. To alleviate this issue, this work introduces an injection-locked ring oscillator-based PLL circuit. The combination of the injection-locking process with the use of ring oscillators allows for the benefit of excellent jitter performance while presenting an extremely low surface area due to an architecture without any inductor. The injection locking principle is addressed, and evidence of its phase noise and jitter improvements are confirmed through measurement results. Indeed, phase noise and jitter enhancements up to 43 dB and 23.3 mUI, respectively, were measured. As intended, this work shows the best integration density compared to recent similar state-of-the-art studies. The whole architecture measures 0.1 mm2 while consuming 34.6 mW in a low-cost 180 nm CMOS technology.

This article presents a non-AC-side voltage sensor control method applied to More Electric Aircraft rectifiers. The control strategy can operate properly over a wide range of frequencies. This strategy calculates the AC supply frequency through an instantaneous phase-locked loop and feeds it back to a dual low-pass filter. The reconstructed rectifier-side voltage is filtered using two low-pass filters with different scale factors. Then, the values of the two filter outputs are subtracted and the effect of the DC bias due to the initial value of the integration is eliminated. The subtracted value is amplitude-phase compensated to calculate the virtual flux value. The phase angle can then be calculated from the virtual flux value. This phase angle is used for the implementation of the voltage-oriented vector control and as an input to the instantaneous phase-locked loop. Simulation and experimental results show that the use of dual low-pass filters under different frequency conditions improves the speed and accuracy of virtual flux estimation and eliminates DC-side bias errors.

In grid-connected inverter systems, the Phase-Locked Loop (PLL) is fundamental for achieving and maintaining precise synchronization between the inverter and the electrical grid. Developing an efficient and robust PLL is essential to ensure reliable operation, particularly in the presence of abnormal grid conditions. Among the existing synchronization methods, the Synchronous Reference Frame-based PLL (SRF-PLL) is widely adopted due to its robust performance; however, it suffers from degraded accuracy under unbalanced voltage conditions. To address this limitation, the Second-Order Generalized Integrator-Quadrature Signal Generator (SOGI-QSG) was proposed in previous studies as an alternative approach. Despite its advantages, the SOGI-PLL exhibits weak filtering capability for lower-order harmonics and remains sensitive to DC offset, both of which can affect synchronization quality. As a result, numerous advanced PLLs based on SOGI-QSG have been proposed in the literature to address SOGI-QSG limitations by enhancing DC offset rejection, filtering capability, and dynamic response. This article provides a comprehensive assessment of various three-phase PLLs based on SOGI-QSG under unbalanced grid conditions, focusing on peak-to-peak frequency error, filtering performance, and DC offset rejection. The operational principles and mathematical models of each technique are discussed, and their performances are validated using MATLAB/Simulink (R2025b). The results show that the SRF-PLL exhibits oscillatory behavior under unbalanced conditions, whereas the PLLs based on SOGI-QSG demonstrate stable synchronization with different trade-offs between filtering strength and dynamic response. Therefore, the selection of the appropriate PLLs based on SOGI-QSG depends on the priorities of the specific application.

In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock frequencies are carefully designed to prevent electromagnetic interference. However, as global navigation satellite system becomes more prevalent, integer-N phase-locked loops face new challenges in generating clocks within the shrinking frequency bands due to large frequency steps determined using a reference clock. To address it, replacing integer-N phase-locked loops with fractional-N phase-locked loops is required. This topic has not been discussed extensively, but it is a practical issue that requires consideration due to its potential impact on development costs. This is why we developed an attachable fractional divider. Our developed divider can efficiently transform integer-N phase-locked loops into fractional-N phase-locked loops, achieving low jitter degradation of 0.35 psrms and a low fractional spur of −69.3 dBc. Thanks to its attachable design, it expedites time-to-market. Regarding mass production, ensuring immunity to process, voltage, and temperature variations is a significant concern. We introduce the circuit techniques employed in the developed fractional divider for immunity to process, voltage, and temperature variations. Subsequently, we provide a comprehensive set of measurement results. The frequency differences over process variations in fractional-N mode is 6.14 ppm. Power supply and temperature dependances are extremely small in spread-spectrum clocking mode. This article illustrates that the developed fractional divider enhances both time-to-market and product reliance.