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A power clamp circuit, which has good immunity to false trigger under fast power-on conditions with a 20 ns rising edge, is proposed in this paper. The proposed circuit has a separate detection component and an on-time control component which enable it to distinguish between electrostatic discharge (ESD) events and fast power-on events. As opposed to other on-time control techniques, instead of large resistors or capacitors, which can cause a large occupation of the layout area, we use a capacitive voltage-biased p-channel MOSFET in the on-time control part of the proposed circuit. The capacitive voltage-biased p-channel MOSFET is in the saturation region after the ESD event is detected, which can serve as a large equivalent resistance (~106 Ω) in the structure. The proposed power clamp circuit offers several advantages compared to the traditional circuit, such as having at least 70% area savings in the trigger circuit area (30% area savings in the whole circuit area), supporting a power supply ramp time as fast as 20 ns, dissipating the ESD energy more cleanly with little residual charge, and recovering faster from false triggers. The rail clamp circuit also offers robust performance in an industry-standard PVT (process, voltage, and temperature) space and has been verified by the simulation results. Showing good performance of human body model (HBM) endurance and high immunity to false trigger, the proposed power clamp circuit has great potential for application in ESD protection.

A novel, area-efficient transient power-rail electrostatic discharge（ESD） clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse（TLP） test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.

introduces several TLU issues in power‐rail ESD clamp circuits fabricated in both low‐voltage (LV) and high‐voltage (HV) 40‐V COMS processes. In LV CMOS process, although the TLU‐free ESD‐clamp circuit can be easily designed by placing double guard rings to surround each MOS devices, a specific “TLU‐like” failure would still occur due to the latch‐on state of ESD‐clamping NMOS under the system‐level ESD test. In HV CMOS process, the bottleneck is that the latchup holding voltage is generally much smaller than the HV nominal operating voltage, thus inevitably leading to TLU risks in HV power‐rail ESD clamp circuits. In addition to the clarification of TLU‐related issues in the power‐rail ESD clamp circuits, the investigation and design of TLU‐free power‐rail ESD clamp circuits are also introduced. These TLU‐free power‐rail ESD clamp circuits can guarantee robust ESD immunity without suffering TLU or any TLU‐like danger in both LV and HV CMOS ICs.

This work presents the design of a novel static-triggered power-rail electrostatic discharge (ESD) clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit (TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current ( I leak ) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.

introduces several special layout issues for latchup prevention. Neglecting these layout issues could draw the unanticipated latchup danger, including latchup between two power domains, between power-pins and grounded N+/N-well, and between two adjacent I/O cells, etc. The ESD-coupled diodes between separated power lines can also lead to the unexpected latchup. Direct connection between I/O pads and the N+/P+ diffusions in internal circuits could easily initiate latchup in internals circuits. Additionally, if the power-rail ESD clamp circuit is very close to the I/O pads, ESD-clamping NMOS could be unexpectedly turned on during the negative trigger current test, probably initiating the latchup in the nearby internal circuits. The corresponding solutions to these unexpected latchup issues are also introduced. By using these IC designers could prevent the possible design mistakes, eliminate the waste of masks and wafers, and decrease the time to market for products.

Possessing the ability to noninvasively elicit brain circuit activity yields immense experimental and therapeutic power. Most currently employed neurostimulation methods rely on the somewhat invasive use of stimulating electrodes or photon-emitting devices. Due to its ability to noninvasively propagate through bone and other tissues in a focused manner, the implementation of ultrasound (US) represents a compelling alternative approach to current neuromodulation strategies. Here, we investigated the influence of low-intensity, low-frequency ultrasound (LILFU) on neuronal activity. By transmitting US waveforms through hippocampal slice cultures and ex vivo mouse brains, we determined LILFU is capable of remotely and noninvasively exciting neurons and network activity. Our results illustrate that LILFU can stimulate electrical activity in neurons by activating voltage-gated sodium channels, as well as voltage-gated calcium channels. The LILFU-induced changes in neuronal activity were sufficient to trigger SNARE-mediated exocytosis and synaptic transmission in hippocampal circuits. Because LILFU can stimulate electrical activity and calcium signaling in neurons as well as central synaptic transmission we conclude US provides a powerful tool for remotely modulating brain circuit activity.

For new renewable clean energy, triboelectric nanogenerators (TENGs) have shown great potential in response to the world energy crisis. Nevertheless, the alternating-current signal generated by a TENG needs to be converted into a direct-current signal to be effective in applications. Therefore, a power management circuit, comprising a clamp rectifier circuit and a mechanical switch, is proposed for the conversion and produces a signal having a low ripple coefficient. The power management circuit adopts a clamp circuit as the rectifier circuit to increase the rectified voltage, and reduces the loss resulted from the components by reducing the use of discrete components; the electronic switch in the buck regulator circuit is replaced with a mechanical switch to reduce cost and complexity. In a series of experiments, this power management circuit displayed a stable output voltage with a ripple voltage of 0.07 V, crest factor of 1.01, and ripple coefficient of 2.2%. The TENG provides a feasible method to generate stable electric energy and to supply power to low-consumption electronic devices.

Gallium nitride (GaN) devices switch faster than silicon devices, making them more vulnerable to significant switching oscillations. To reduce the effect of crosstalk in GaN High Electron Mobility Transistor (GaN HEMT)-based bridges, this paper introduces a passive clamp circuit to restrain gate source voltage oscillations. Utilizing resistive and capacitive diodes, as well as diodes and transistors, a bootstrap driving circuit can be established. This circuit forms a low impedance Miller current path from the driving IC to the GaN device, which decreases the impact of both positive and negative crosstalk. Employing resistive and capacitive diodes, as well as diodes and transistors, a bootstrap driving circuit can be established. This circuit creates a low impedance Miller current path from the driving IC to the GaN device, reducing the effects of the positive and negative crosstalk. This method, which mostly uses passive components, simplifies the circuit design in comparison to other passive gate driver methods. Through dual-pulse testing with a GS661008P, its capacity to suppress positive and negative crosstalk in GaN devices has been confirmed.

A high conversion ratio DC-DC converter is crucial for fuel cell electric vehicles (FCEV). A fuel cell-based non-isolated high gain integrated DC-DC converter for electric vehicles is proposed in this paper. The system comprises an interleaved boost converter (IBC) at the source end, a switched capacitor cell, coupled inductors, a passive clamp circuit, and a voltage multiplier circuit (VMC). Its significance is to achieve the voltage conversion gain of 12.33 at a conversion ratio of 0.45. The idea is to use a proton exchange membrane fuel cell to power electric vehicles through a high-gain DC-DC converter. The use of an ineffective MPPT can result in lower energy conversion efficiency. Thus, this system incorporates a maximum power point tracking (MPPT) controller based on a neural network, which relies on the radial basis function network (RBFN) algorithm to track the maximum power point of the PEMFC accurately. The comparative study of the fuel cell electric vehicle (FCEV) structure with the RBFN-based MPPT technique was evaluated with that of the fuzzy logic technique using the MATLAB/Simulink platform (R2021b (MATLAB 9.11)). A 1.5 kW experimental prototype is designed with a switching frequency of 10 kHz to validate the design analysis, and its pursuance is compared between RBFN and FLC-based controllers. This manuscript will be a significant contribution towards evidencing a sustainable environment.

Power electronic devices are essential components of high-capacity industrial converters. Accurate assessment of their power loss, including switching loss and conduction loss, is essential to improving electrothermal stability. To accurately calculate the conduction loss, a drain–source voltage clamp circuit is required to measure the on-state voltage. In this paper, the conventional drain–source voltage clamp circuit based on a transistor is comprehensively investigated by theoretical analysis, simulations, and experiments. It is demonstrated that the anti-parallel diodes and the gate-shunt capacitance of the conventional drain–source voltage clamp circuit have adverse impacts on the accuracy and security of the conduction loss measurement. Based on the above analysis, an improved drain–source voltage clamp circuit, derived from the conventional drain–source voltage clamp circuit, is proposed to solve the above problems. The operational advantages, physical structure, and design guidelines of the improved circuit are fully presented. In addition, to evaluate the influence of component parameters on circuit performance, this article comprehensively extracts three electrical quantities as judgment indicators. Based on the working mechanism of the improved circuit and the indicators mentioned above, general mathematical analysis and derivation are carried out to give guidelines for component selection. Finally, extensive experiments and detailed analyses are presented to validate the effectiveness of the proposed drain–source voltage clamp circuit. Compared with the conventional drain–source voltage clamp circuit, the improved drain–source voltage clamp circuit has higher measurement accuracy and working security when measuring conduction loss, and the proposed component selection method is verified to be reasonable and effective for better utilizing the clamp circuit.