Explore the vast range of titles available.

Using reconfigurable intelligent surfaces (RISs) to improve the coverage and the data rate of future wireless networks is a viable option. These surfaces are constituted of a significant number of passive and nearly passive components that interact with incident signals in a smart way, such as by reflecting them, to increase the wireless system's performance as a result of which the notion of a smart radio environment comes to fruition. In this survey, a study review of RIS‐assisted wireless communication is supplied starting with the principles of RIS which include the hardware architecture, the control mechanisms, and the discussions of previously held views about the channel model and pathloss; then the performance analysis considering different performance parameters, analytical approaches and metrics are presented to describe the RIS‐assisted wireless network performance improvements. Despite its enormous promise, RIS confronts new hurdles in integrating into wireless networks efficiently due to its passive nature. Consequently, the channel estimation for, both full and nearly passive RIS and the RIS deployments are compared under various wireless communication models and for single and multi‐users. Lastly, the challenges and potential future study areas for the RIS aided wireless communication systems are proposed. This article provides a general survey of the state of the art reconfigurable intelligent reflecting surfaces (RIS) research. It discusses the principle of RIS in terms of design and operations.

The analysis and verification of the integration of hardware and software components is challenging. Traditional HDL simulators, which are often slow and provide low‐level analysis tools, are not always effective for simulating the software of processor‐based systems. This work presents an interactive co‐simulation framework that enhances students' understanding of computer architecture concepts typically obscured by hardware intricacies. This framework facilitates a unified environment for iterative design, enabling detailed analysis and generation of reports and traces to identify system performance, bottlenecks, and find implementation errors. By prioritizing analysis features over performance, this framework serves as a valuable tool for educational purposes and comprehensive examination of the interactions between hardware and software. This work introduces an interactive co‐simulation framework that helps students understand computer architecture by bridging hardware and software analysis. Prioritizing detailed analysis over performance, it provides an integrated environment for iterative design, performance evaluation, and debugging.

An intelligent reflecting surface (IRS)‐aided visible light secure communication system is investigated. In order to improve its security performance, a power splitting scheme is adopted at the light‐emitting diodes. In contrast to most current research on the physical‐layer security in IRS‐aided visible light secure communication systems where secrecy rate or secrecy capacity maximization problems subject to various resource constraints were formulated, this letter takes the reliability of secure transmission into account. The closed‐form expression of secrecy outage probability is derived based on the statistical characteristics of the signal‐to‐noise ratio of the legitimate user, and the effects of light‐emitting diodes and IRS parameters and power splitting ratio on the secrecy outage probability are validated through simulations. Contrary to most research that primarily focuses on formulating secrecy rate or secrecy capacity maximization problems in intelligent reflecting surface‐assisted visible light secure communication systems, this study innovatively emphasizes the reliability of secure transmissions. To enhance security performance, a novel power splitting scheme is implemented at the light‐emitting diodes. Furthermore, the research derives a closed‐form expression for the secrecy outage probability based on the statistical characteristics of the legitimate user's signal‐to‐noise ratio, and it validates the impact of light‐emitting diode, intelligent reflecting surface parameters, and the power splitting ratio through comprehensive simulations.

Reconfigurable intelligent surfaces (RISs) have attracted a great deal of interest due to the potential contributions to the next‐generation wireless networks. This letter proposes an enhancement to the physical layer security (PLS) of a multi‐hop RIS‐assisted underwater optical wireless communication (UOWC) system. Owing to the complexity of the underwater environment, a security‐based adaptive RIS (SA‐RIS) clustering strategy, which aims to reflect optical signals among clusters to improve the performance of the overall system, is evaluated. By combining the underwater channel model, the closed‐form expressions of probability density function (PDF) and cumulative distribution function (CDF) are derived. Moreover, by increasing the numbers of RIS clusters, the performance metrics such as secrecy outage probability (SOP) and average secrecy capacity (ASC) are evaluated under different scenarios. The obtained results demonstrated that, in contrast to the case without preventing the eavesdropper, the proposed strategy in evasion scenarios could improve the SOP significantly. It can be concluded that the system secrecy performances are further improved by assigning different RIS clusters with proper channel quality. A multi‐hop RIS‐assisted underwater optical wireless communication (UOWC) system adopting the SA‐RIS clustering strategy, which aims to realize the efficient utilization of channel transmission strategy, is proposed in this letter. Closed‐form expressions of the PDF and CDF based on the proposed RIS‐assisted UOWC systems are derived in terms of SNR. The numerical results show that at high SNR values, a higher secrecy capacity value can be achieved with more RIS clusters where the results further corroborate the feasibility of the multi‐hop RIS‐assisted UOWC system.

Chiplet‐based systems leveraging a domain‐specific reusable interposer (DSRI) technology achieve superior performance, power, and cost (PPC) advantages. This paper proposes AutoDSRI, an automated framework for chiplet generation and topology synthesis (TS) in DSRI design. AutoDSRI introduces a hierarchical graph partitioning method, first partitioning domain‐generic esults show an average of 29.18% improvement in PPC over traditional methods. This paper proposes AutoDSRI, an automated framework for chiplet generation and TS in chiplet‐based design. AutoDSRI introduces a hierarchical graph partitioning method and constructs a MCG to simplify the topology.

This letter presents a high‐ Q tunable waveguide (WG) filter with constant absolute bandwidth (CABW). By adjusting the penetration depth of a single dielectric tuning element into the filter, frequency tuning is readily obtained without a complicated mechanism. Modified cavity perturbation theory (CPT) is adopted for the first time to deduce the quantitative relationship between the penetration depth and resonant frequency. At the same time, the tuning element also plays a vital role in realising innovative inter‐resonator (IR) coupling and input‐output (IO) coupling structures, combined with the configuration of double septa to ensure the CABW and IO port impedance matching. Finally, to validate the proposed concept, a prototype of a fifth‐order inline tunable WG filter is implemented, which has a tuning range of 8% from 18.2 to 19.7 GHz and the 1‐dB bandwidth variation is maintained within 315 ± 15 MHz. Measured results match the simulated ones very well, which show that the insertion losses are less than 0.6 dB and the return losses are better than 20 dB for all tuned passbands. The high performance of the proposed tunable WG filter makes it very suitable for the applications of 5G/6G millimetre‐wave backhaul or satellite telecommunication.

A novel 3‐bit frequency‐reconfigurable antenna (FRA) with miniaturized dimensions is realized with a meander line. The frequency reconfiguration of the antenna is achieved by introducing N Radio Frequency (RF) PIN diodes into the meander line. The related parts of the meander line with different lengths are bypassed or included into the antenna by switching on or off the diodes, resulting in 2N switchable size lengths of the antenna and equally spaced operating frequencies. A 3‐bit reconfigurable meander‐line antenna (N = 3) is designed, and the simulated and measured results agree well. The antenna provides 8 (23) independent and switchable states, with the operating frequencies covering a wide switchable frequency range from 1.04 to 1.51 GHz and the working bandwidths varying from 80 to 150 MHz. The number of working bandwidth states is maximized, considering the number of switches used. Moreover, the results reveal an acceptable peak gain of 1.59 dBi in terms of the miniaturized total dimension of 0.17 λg × 0.07 λg (λg is the guided wavelength at the lowest working frequency), which is more compact than several published FRAs. This figure gives the circuit and topology of the reconfiguable antenna.

A compact microstrip multifunctional reconfigurable filtering power divider (FPD) is proposed based on varactor‐loaded three‐parallel‐coupled line section (TLCS) in this letter. Continuously tunable third‐order filtering power division response with two transmission zeros (TZs) including centre frequency (CF), bandwidth (BW) and power division ration (PDR) is successfully attained by varying the external and internal coupling through loading varactors into a three‐parallel‐coupled line topology. For validation, a prototype is implemented. The results indicate that the CF can be tuned from 0.46 to 0.8 GHz, a tunable 3‐dB BW of 80 to 190 MHz is exhibited with better than 17‐dB return loss and higher than 15‐dB in‐band isolation. In addition to the CF and BW tunability, the power division ratio (PDR) for the presented FPD can also be adjusted from 1:1 to 1:5. Additionally, a compact size is realized with only 0.12λg × 0.16λg. A compact microstrip multifunctional reconfigurable filtering power divider (FPD) is proposed based on varactor‐loaded three‐parallel‐coupled line section (TLCS) in this letter. Continuously tunable third‐order filtering power division response with two transmission zeros (TZs) including centre frequency (CF), bandwidth (BW) and power division ration (PDR) is successfully attained by varying the external and internal coupling through loading varactors into a three‐parallel‐coupled line topology.

In this letter, a beam downtilt reconfigurable linear antenna array is presented for the demand of the electrical downtilt of 5G/6G macro base station antennas. The antenna is capable of fine‐angle beam direction reconfiguration, allowing for improved adaptability in various environmental conditions. A hierarchical network design is employed, which incorporates essential elements such as phase shifter modules, power dividers, and couplers. These fundamental components are used to construct a five‐element reconfigurable feeding network for the antenna array. The designed network ensures stable phase shifts and excellent impedance matching performance. By integrating the feeding network with the antenna elements, the system achieves electronic beam tilt adjustment across four states, enabling the linear array to tilt downward within a range of 6–12° around 3.5 GHz. This design provides enhanced beam control, making it suitable for next‐generation macro base station applications in 5G and 6G networks. To verify the proposed design, a prototype was fabricated and tested. From the overall structure of the linear array, it is evident that the array consists of the five‐element antenna array, cascaded with the reconfigurable feeding network.

Signature-based authentication is used often to authenticate hardware intellectual property (IP) when it is reused on a plug-and-play system-on-chip. A signature embedded in the functional/test component of a hardware IP can easily be verified as it can be generated and observed as functional/scan output of the hardware IP for a certain input key vector. An existing scan-based approach for embedding signature inserts signature through reordering of scan cells in a single scan (SS) chain. However, it is not applicable to the recent reconfigurable scan architectures having reduced test application time. We propose a scheme for embedding two distinct signatures separately in a reconfigurable scan architecture and verifying those without conflict from the packaged chip by using two distinct test modes of the reconfigurable architecture: namely, scan tree mode and SS mode. The two signatures may include one from logic IP source and the other from physical IP source. The overhead in both routing and power has been minimised in our scheme. Experimental results on design overhead and robustness for ISCAS89 benchmarks are very encouraging.