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In the current situation of the Internet of Things (IoT) with its billions of interconnected devices, security in this low-resource environment is paramount. A Physical Unclonable Function (PUF) is a very useful cryptographic primitive which allows us to extract unique information from a particular device in a non-reproducible way. This allows us to use a PUF in cryptography for authentication or secret-key generation. Ring Oscillators (ROs) and Transient Effect Ring Oscillators (TEROs) are oscillating structures used in both FPGAs and ASICs to build PUFs. In this paper we present an FPGA implementation of a PUF based on what we call the “TERORO” cell (TERO + RO), which is a hybrid structure that allows us to use the different functionalities of both RO and TERO in a single building block. We assess all the possible methods of extracting bits of information from the PUF based on TERORO cells. Finally, we tested the circuit and presented experimental results in terms of its uniqueness, uniformity, and reliability. In RO-counter mode, we obtain 49.74% uniqueness, 54.66% uniformity, and 97.81% reliability across devices, while TERO-based XOR mixing achieves 52.83% uniformity, 45.79% uniqueness, and 93.15% reliability. The FPGA footprint is 142 LUTs, 36 registers, and 82 slices.

Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100°C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs.

Any cryptographic system strongly relies on randomness to ensure robust encryption and masking methods. True Random Number Generators play a fundamental role in this context. The National Institute of Standards and Technology (NIST) and the Bundesamt für Sicherheit in der Informationstechnik (BSI) provide guidelines for designing reliable entropy sources to fuel cryptographic Random Bit Generators. This work presents a highly parameterized, open-source implementation of a TRNG based on ring oscillators, complemented by an optimized Keccak conditioning unit. The design process is accompanied by a thorough study of the relevant literature and standards, specifying the requirements for reliable entropy sources in cryptographic systems. The design of the TRNG proposed in this paper aims to strike a balance between area, throughput, power consumption, and entropy, while adhering to these guidelines. The proposed design has undergone extensive testing and validation and has successfully passed the NIST SP 800-22, NIST SP 800-90B, and BSI AIS-31 tests, achieving a min-entropy per bit of 0.9982 (NIST) and 0.9998 (BSI).

We demonstrate the utility of machine learning algorithms for the design of oscillatory neural networks (ONNs). After constructing a circuit model of the oscillators in a machine-learning-enabled simulator and performing Backpropagation through time (BPTT) for determining the coupling resistances between the ring oscillators, we demonstrate the design of associative memories and multi-layered ONN classifiers. The machine-learning-designed ONNs show superior performance compared to other design methods (such as Hebbian learning), and they also enable significant simplifications in the circuit topology. We also demonstrate the design of multi-layered ONNs that show superior performance compared to single-layer ones. We argue that machine learning can be a valuable tool to unlock the true computing potential of ONNs hardware.

This paper introduces the electronic interface for a capacitive airborne particle matter detector. The proposed circuit relies on two matched ring oscillators and a mixer to detect the frequency difference induced by the deposition of a particle onto an interdigitated capacitor, which constitutes the load of one of the oscillators. The output of the mixer is digitized through a simple counter. In order to compensate the oscillation frequency offset of the two ring oscillators due to process and mismatch variations, a capacitive trimming circuit has been implemented. The sensor is connected to host through an I2C interface for communication and configuration. The sensor has been implemented using a standard 130-nm CMOS technology by STMicroelectronics and occupies 0.12-mm2 die area. Experimental measurements using talcum powder show a sensitivity of 60 kHz/fF and a 3σ resolution equal to 165 aF.

In this paper, we propose a method to enhance the performance of a random number generator (RNG) that exploits ring oscillators (ROs). Our approach employs additional phase detectors to extract more entropy; thus, RNG uses fewer resources to produce bit sequences that pass all statistical tests proposed by National Institute of Standards and Technology (NIST). Generating a specified number of bits is on-demand, eliminating the need for continuous RNG operation. This feature enhances the security of the produced sequences, as eavesdroppers are unable to observe the continuous random bit generation process, such as through monitoring power lines. Furthermore, our research demonstrates that the proposed RNG’s perfect properties remain unaffected by the manufacturer of the field-programmable gate arrays (FPGAs) used for implementation. This independence ensures the RNG’s reliability and consistency across various FPGA manufacturers. Additionally, we highlight that the tests recommended by the NIST may prove insufficient in assessing the randomness of the output bit streams produced by RO-based RNGs.

In this paperâ, âan inductor-lessâ, âhigh frequency tuning range and low power CMOS voltage controlled oscillator (VCO) is presentedâ. âThe VCO can be implemented in 0.18 µm CMOSâ, âwith 1.8 V supply voltageâ. âBy using a novel structureâ, âa high frequency tuning rangeâ, âlow phase noise and low power consumption VCOâ, âis obtainedâ. âIn order to increase the frequency tuning rangeâ, âan active inductor is usedâ. âIn additionâ, âdeep triode region transistors are employed to enhance the swing of the output voltageâ. âBy using the results of simulation with HSPISE softwareâ, âthe tuning rangeâ, âphase noise and power consumption are 5.49-9.6 GHzâ, -â146 dBc/Hz and 5.99 mWâ, ârespectivelyâ.

In building spiking neural networks for edge devices, low power consumption and time scale matching with the input signal are essential characteristics for their analog implementation. In each node of the neural network, an activation function should be implemented to achieve nonlinearity between input spike frequency and output spike frequency. However, the conventional analog implementation often achieves nonlinearity in the voltage domain rather than in the spike frequency domain and consumes considerable power. In this study, a nonlinear frequency-conversion circuit based on a current-starved ring oscillator is proposed. In order to design nonlinearity in the frequency domain, the supply current for the ring oscillator is controlled as a function of input spike frequency. As a result, a hyperbolic-tangent nonlinearity is achieved in the simulation with the TSMC 180 nm process. Furthermore, the supply current is controlled in an extremely low range to achieve low power consumption of 0.2 nW and several hundred millisecond time constants, which are suitable for processing data with similar time scales such as biomedical data, environmental vibration, and so on.

The objective of the proposed work is to demonstrate the use of a hybrid approach for the design of a voltage-controlled oscillator (VCO) which can lead to higher performance. The performance is improved in terms of the tuning range, frequency of oscillation, voltage swing, and power consumption. The proposed hybrid VCO is designed using an active load common source amplifier and current starved inverter that are cascaded alternatively to achieve low power consumption. The proposed VCO achieves a measured phase noise of -74 dBc/Hz and a figure of merit (FOM) of -152.6 dBc/Hz at a 1 MHz offset when running at 5.1 GHz frequency. The hybrid current starved-current starved VCO (CS-CS VCO) consumes a power of 289 µW using a 1.8 V supply and attains a wide tuning range of 96.98%. Hybrid VCO is designed using 0.09 µm complementary metal–oxide–semiconductor (CMOS) technology. To justify the robustness, reliability, and scalability of the circuit different corner analysis is performed through 500 runs of Monte-Carlo simulation.

ElectroMagnetic Fault Injection (EMFI) attacks have garnered noteworthy attention in the world of embedded secure devices due to the optimal balance between the attack effectiveness and the setup requirements. Since Ring Oscillators (ROs) can be critical components for secure primitives such as True Random Number Generators (TRNGs), Physical Unclonable Functions (PUFs) and on-chip voltage or temperature sensors, their response to this potent threat needs to be fully investigated. In this paper, we contribute to a deeper understanding of EMFI faults by performing single EM pulsed fault injections on ROs implemented in Field-Programmable Gate Arrays (FPGAs). The fault models proposed in the state of the art, such as the Sampling Fault Model and the Timing Fault Model, mainly refer to synchronous logic and are not tuned for asynchronous combinational logic in a loop. Our findings reveal that harmonic locking explains the occurrence of harmonic errors with variable characteristics depending on the different EM pulse settings, the RO placement within the FPGA chip and the manufacturing properties of the FPGA. These findings improve our understanding of EMFI’s impact on different architectures and can be leveraged to design more robust hardware implementations against this attack.