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Moore's law : the life of Gordon Moore, Silicon Valley's quiet revolutionary
\"A chemist and founder of Intel, Gordon Moore played a major role in revolutionizing technology and shaping the growth and reach of Silicon Valley. The story of the man--an inventor and businessman whose influence on the world is at least as great as Thomas Edison's, Henry Ford's, or Bill Gates's--has never before been told ... [In this book], Arnold Thackray sheds light on Gordon Moore, gives context to the technologies and world of high-tech power he helped to develop, and provides [an] ... introduction to the history and science of the silicon transistor, the technological building block that has transformed commercial business, defense strategies, and the everyday lives of individuals around the globe\"-- Provided by publisher.
Book
A high‐performance asynchronous readout circuit with cascade function for a neural recording micro‐electrode array
The data‐driven machine learning technology used for neural decoding emphasizes the requirements of in vivo and in vitro neural signal acquisition with high spatial and temporal resolution. However, micro‐electrode arrays (MEAs) that simultaneously achieve high spatial and temporal resolution neural signal acquisition are not yet available. Meanwhile, the high data bandwidth of large‐scale MEA brings challenges in power consumption, data transmission, storage, and neural signal processing. This research aims to improve the spatial and temporal resolution of MEA, reduce the cost and time of large‐scale MEA customization through cascading, and reduce the bandwidth of large‐scale MEA through spike compression. Firstly, based on in‐pixel spike detection, a row‐based neural spike readout mechanism and related array circuit to improve the neural spike readout performance and temporal resolution of neural signal acquisition is proposed. To further enhance the spatial resolution and reduce the risk of large‐scale MEA fabrication, the cascading capability of the readout circuit is explored. Lastly, spatial correlation‐based neural spike encoding is proposed to reduce the data bandwidth, achieving a 5.2× compression rate. This is a study on implementing large‐scale MEA through cascaded readout circuits and novel study to utilize the spatial correlation between detected neural spikes for further compression. This research focuses on enhancing micro‐electrode array's (MEA) spatial and temporal resolution for neural decoding, exploring cascading readout circuits to customize large‐scale MEAs efficiently, and reducing data bandwidth through spike compression, achieving a significant compression rate by utilizing spatial correlation between detected neural spikes.
Journal Article
AlN/AlGaN HEMTs on AlN substrate for stable high-temperature operation
An AlN/AlGaN high-electron-mobility transistor (HEMT) fabricated on a free-standing AlN substrate is demonstrated. A metal stack, composed of Zr/Al/Mo/Au, was found to show low contact resistivity for source and drain ohmic contacts. The fabricated AlN/AlGaN HEMT exhibited a maximum drain current of 38 mA/mm with a threshold voltage of −3.4 V. Negligible drain current degradation was observed at temperatures from 300 to 573 K, demonstrating that an AlN/AlGaN approach on an AlN substrate is promising for stable high-temperature operation.
Journal Article
From Technology to Strategy: The Evolving Role of Smart Grids and Microgrids in Sustainable Energy Management
This study presents a comprehensive bibliometric review of 136 academic publications on smart grids, microgrids, and semiconductor technologies in the context of sustainable energy management. Data were collected from the Web of Science Core Collection and analyzed using VOSviewer to identify intellectual structures, thematic clusters, and research trajectories. The results demonstrate the increasing prominence of semiconductor-enabled solutions in advancing renewable energy integration, grid optimization, and energy storage systems. Five major research themes are identified: renewable energy and smart grid integration; distributed microgrid systems; optimization models; control strategies; and system-level resilience and cybersecurity. The analysis reveals a temporal evolution from foundational engineering (2020–2021) to intelligent, digitally enhanced energy systems (2022–2025), with a growing emphasis on electric mobility, digital twins, and advanced energy management techniques, such as convex optimization. Beyond mapping trends, this study underscores critical research gaps in the non-English literature, multi-database integration, and practical deployment. The findings provide actionable insights for researchers, policymakers, and industry leaders by highlighting technological maturity, real-world applications, and strategic implications for energy transition. By aligning digital intelligence, semiconductor innovation, and sustainable energy goals, this review advances a forward-looking agenda for resilient and equitable energy systems.
Journal Article
Fabrication of 150‐nm AlGaN/GaN field‐plated High Electron Mobility Transistors using i ‐line stepper
This article reports a high throughput 150‐nm‐gate AlGaN/GaN high electron mobility transistor (HEMT) process using i‐line stepper lithography and a thermal reflow technique. Optimizing thermal reflow conditions, fabrication of a 150‐nm gate structure was successfully realized with the initial resist opening of 0.7 μm. AlGaN/GaN field‐plated HEMTs were fabricated on a semi‐insulating SiC substrate by using this process. In spite of unoptimized structures, fabricated 150‐nm gate devices exhibited the maximum drain current of 0.65 A/mm and the gate‐drain breakdown voltage exceeding 200 V. Based on cold HEMT extraction measurements, the average gate length of 187 nm and the standard deviation of 30 nm were obtained on a quarter 4‐in. wafer.
Journal Article
Application of Semiconductor Technology for Piezoelectric Energy Harvester Fabrication
In this paper, we propose the application of semiconductor technology processes to fabricate integrated silicon devices that demonstrate the piezoelectric energy harvesting effect. The harvesting structure converts thermal energy into electricity using a piezoelectric transducer, which generates electrical signals owing to the dynamic bending under pressure caused by the explosive boiling of the working fluid within the harvester. The challenges of previous works that included complex manufacturing processing and form limitations were addressed by the use of semiconductor technology based on laser beam processing, which led to simplification of the device’s fabrication. The electrical characterization of the fabricated harvester prototype proved its functionality in energy conversion and potential for integration with a step-up converter or power management integrated circuit (PMIC) generating stable impulses ranging from 0.4 to 1.5 V at a frequency of 7 Hz.
Journal Article
Reversible priority encoder design and implementation using quantum-dot cellular automata
Quantum-dot cellular automata (QCA) are the potential alternative to complementary metal–oxide–semiconductor-based technology. Ideally, zero power dissipation can be achieved with the help of reversible computing. In this study, a novel design of a reversible priority encoder based on QCA is proposed. The basic building blocks for the design are Toffoli and BJN gates. The proposed design is verified by the QCA designer simulator. The performance analysis of the reversible priority encoder is performed based on the simulation results. The proposed encoder not only overcomes the problem of the messy code but also declines the amount of heat energy dissipation through reversible logic. The proposed reversible circuit could be a major component in future wireless communication because reversible logic accounts for zero loss of information. The estimation of power consumption by proposed QCA circuits is explored that implies QCA can be an ideal platform to implement reversible circuits. The relationship with recently proposed work is also discussed.
Journal Article
A Novel Approach of −80 °C Cascade Refrigeration System Using Non-Flammable Quaternary Refrigerants for Semiconductor Process Applications
Ultra-low temperature chillers have seen increasing demand with the advancement of semiconductor technology. Mixed refrigerant (MR) cascade refrigeration systems (CRSs) are widely utilized for their stability and high cooling performance at low temperatures. Extensive research has been conducted on optimizing MR, which has a significant impact on CRS performance. However, most previous studies have either fixed the system pressure or used the refrigeration effect as the sole performance indicator. This did not account for the potential of achieving higher performance with an optimal MR composition at the same target temperature. In this study, a detailed parametric analysis was performed to investigate how the mass fractions of high-, mid-, and low boiling point refrigerants affect the coefficient of performance (COP) and exergy in ultra-low temperature CRSs without fixing the suction pressure. The analysis revealed that at the point of maximum COP, the refrigeration effect was relatively low, highlighting the limitations of using the refrigeration effect alone as a performance indicator. Additionally, COP was found to inversely correlate with total exergy destruction. As cascade temperature increases, COP tends to decrease, emphasizing the need for appropriate cascade temperature selection for MR CRS performance. This study introduces a novel approach to optimizing MR composition under various operating conditions, contributing to the advancement of ultra-low temperature CRSs.
Journal Article
Metal organic chemical vapour deposition regrown large area GaN‐on‐GaN current aperture vertical electron transistors with high current capability
In this work, a large area current aperture vertical electron transistor (CAVET) is fabricated on bulk GaN substrates grown by metal organic chemical vapour deposition (MOCVD). The current blocking layer (CBL) is formed by low dose Mg‐implantation to allow for MOCVD regrowth under standard growth conditions, which simultaneously serves as an in‐situ annealing process. Small transistors are evaluated regarding gate‐aperture overlap (LGAP) to derive a robust layout in order to suppress source‐drain leakage. Optimized gate‐aperture dimensions are adopted and combined with a common comb structure design and the established gate‐source module of the lateral HEMT to demonstrate a large area CAVET comb structure. The multi‐finger device exhibits an on‐state resistance of RON = 2.15 Ω and a chip area of A = 2 × 2 mm². The large area CAVET reveals a maximum drain current of ID,MAX = 20.1 A at a drain‐source voltage of VDS = 45 V, corresponding to a power of P = 900 W.
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