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The subject of this study is a frequency estimation algorithm suitable for grid-connected power converters placed at a weak coupling point of a three-phase electrical distribution system. An upgraded version of the widely used complex least mean squares (CLMS) algorithm for frequency estimation is introduced to cope with different voltage amplitude unbalance and harmonic distortion levels, both frequently present in power system at distribution level. First, it is suggested that the CLMS algorithm uses only a positive phase-sequence component of voltage vector, the component that is inherently symmetrical and by cancelling the phase unbalance preserves the circular vector trajectory in a two-phase αβ-plane. This study shows that it is even possible to use the positive voltage phase-sequence vector extracted using a constant delay block, thus avoiding potential instability issues in the case of signal frequency feedback loop. Second, possible high signal harmonics and signal measurement noise are both removed using low-pass filters prior to CLMS algorithm deployment. Computer simulations and experiments are performed under a variety of conditions to validate the effectiveness of the proposed technique. Experimental results are achieved using the dataset sampled from the actual three-phase grid voltage at distributed level and with data processing done in the LabVIEW software environment.

We demonstrate a closed-loop Electro-Optical Phase-Locked Loop (EO-PLL) designed to increase the linearity of frequency chirps in Frequency-Modulated Continuous-Wave (FMCW) LiDAR systems, resulting in improved metrological accuracy. The system is fully implemented on an easily accessible FPGA-based digital electronic platform (Red Pitaya STEMlab 125-14). A PC-based UI was developed to facilitate remote real-time control over key system parameters. The proposed closed-loop control reduces the Full-Width Half Maximum (FWHM) in frequency domain to 11 kHz, corresponding to a range resolution of 19.9 mm at a beat frequency of 2.45 MHz. Additionally, the system effectively suppresses disturbances in the modulation signal for frequencies up to 150 kHz, with stabilization settling within a single modulation period. This approach enables the use of lasers with nonlinear modulation slopes in FMCW LiDAR applications, even under fluctuating ambient conditions.

In the realm of signal processing, frequency error stands as a critical challenge that cannot be overlooked, particularly in scenarios characterized by noise disturbances and constantly changing environmental variables, as it significantly undermines the precision of waveform separation. Faced with a spectrum of frequency error phenomena stemming from hardware instability, such as clock drift, transmission distortion, and environmental changes, this paper proposes a waveform separation scheme centered around a core closed-loop control architecture aimed at addressing such challenges. Leveraging the high-performance STM32F407 microcontroller platform, the system harnesses the powerful algorithmic advantages of Fast Fourier Transform (FFT) to precisely locate and delineate the spectral characteristics of signals. Furthermore, we creatively integrate lock-in amplifier technology into the meticulously designed closed-loop control system, coupled with state-of-the-art zero-crossing detection algorithms for in-depth optimization. The research findings demonstrate outstanding signal-to-noise ratio performance within predefined target frequency bands for the separation device based on lock-in amplifier technology, showcasing not only remarkable resilience against interference but also the ability to accurately separate and reconstruct target signal components with high fidelity from complex and dynamic signal environments. This significantly enhances the robustness and accuracy of the entire system.

The propagation of information through signaling cascades spans a wide range of time scales, including the rapid ligand-receptor interaction and the much slower response of downstream gene expression. To determine which dynamic range dominates a response, we used periodic stimuli to measure the frequency dependence of signal transduction in the osmo-adaptation pathway of Saccharomyces cerevisiae. We applied system identification methods to infer a concise predictive model. We found that the dynamics of the osmo-adaptation response are dominated by a fast-acting negative feedback through the kinase Hog1 that does not require protein synthesis. After large osmotic shocks, an additional, much slower, negative feedback through gene expression allows cells to respond faster to future stimuli.

This paper designs a cascading vector tracking loop based on the Unscented Kalman Filter (UKF) for high dynamic environment. Constant improvement in dynamic performance is an enormous challenge to the traditional receiver. Due to the doppler effect, the satellite signals received by these vehicles contain fast changing doppler frequency shifts and the first and second derivatives of doppler frequency, which will directly cause a negative impact on the receiver’s stable tracking of the signals. In order to guarantee the dynamic performance and the tracking accuracy, this paper designs a vector carrier structure to estimate the doppler component of a signal. Firstly, after the coherence integral, the IQ values are reorganized into new observations. Secondly, the phase error and frequency of the carrier are estimated through the pre-filter. Then, the pseudorange and carrier frequency are used as the observations of the main filter to estimate the motion state of the aircraft. Finally, the current state is fed back to the carrier Numerical Controlled Oscillator (NCO) as a complete closed loop. In the whole structure, the cascading vector loop replaces the original carrier tracking loop, and the stable signal tracking of code loop is guaranteed by carrier assisted pseudo-code method. In this paper, with the high dynamic signals generated by the GNSS signal simulator, this designed algorithm is validated by a software receiver. The results show that this loop has a wider dynamic tracking range and lower tracking error than the second-order frequency locked loop assisted third-order phase locked loop in high dynamic circumstances. When the acceleration of carrier is 100 g, the convergence time of vector structure is about 100 ms, and the carrier phase error is lower than 0.6 mm.

A delay lock loop is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on a CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques with good current matching. The delay cell uses the bulk-driven technique and has less power consumption than the conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 μm CMOS process with a supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure.

Distortions of electrocardiograms (ECGs) caused by mandatory high-pass and low-pass analog RC filters in ECG devices are always present. The fidelity of the ECG waveform requires limiting the RC cutoff frequencies of the diagnostic (0.05–150 Hz) and monitoring systems (0.5–40 Hz). However, the use of fixed frequency bands is a compromise between enhanced noise immunity and ECG distortions. This study aims to propose active inverse high-pass and low-pass filters which are able to compensate for distortions in digital recordings of RC-filtered ECGs, thereby overcoming the limitations imposed by analog filtering. A new straightforward design of an inverse high-pass filter (IHPF) uses an integrator as the forward-path gain block, with a feedback loop containing an active digital filter equivalent to the analog RC high-pass filter. In contrast, the inverse low-pass filter (ILPF) employs a constant-gain block in the forward path to ensure stability and prevent phase delay, while its feedback path features an active digital counterpart of the RC low-pass filter. Second-order inverse filters are created by cascading two first-order stages. The proposed filters were validated according to essential performance requirements for electrocardiographs. The low-frequency (impulse) responses of IHPFs with cutoff frequencies of 0.05–5 Hz exhibit no overshoot and undershoot by magnitudes of 0.1–25 µV, well within the ±100 µV compliance limit defined for a test rectangular pulse (3 mV, 100 ms). The high-frequency responses of ILPFs with cutoff frequencies of 10–150 Hz present a relative amplitude drop of only 0.2–2.5%, far below the 10% limit for peak amplitude reduction of a triangular pulse (1.5 mV) with 20 ms vs. 200 ms widths. For any of the eight ECG leads (I, II, and V1–V6) available in the standard signal (ANE20000), the IHPF (0.05–5 Hz) presents ST-segment deviations <5 μV (within the ±25 μV limit) and R- and S-peak deviations <±3.5% (within the ±5% limit). The ILPF (10–150 Hz) preserves R- and S-peak amplitudes with deviations less than −1%. Diagnostic-level recovery of ECG waveforms distorted by first- and second-order analog RC filters in ECG devices is possible with the innovative and comprehensive inverse filter design presented in this study. This approach offers a significant advancement in ECG signal processing, effectively restoring essential waveform components even after aggressive, noise-robust analog filtering in ECG acquisition circuits. Although validated for ECG signals, the proposed inverse filters are also applicable to other biosignal front-end circuits employing RC coupling.

This work presents a novel frequency compensation method for four‐stage CMOS amplifiers, addressing the complexity and instability challenges prevalent in modern low‐voltage, low‐power electronic systems. The proposed approach employs nested differential gain stages combined with a single, compact Miller capacitor at the common output, which enables efficient frequency compensation while minimizing chip area and power consumption. The amplifier benefits from the topological advantages of differential stage integration, allowing the Miller effect to be virtually amplified across multiple feedback loops and facilitating the use of a smaller compensation capacitor. The linear transfer function (TF) of the design is meticulously derived through symbolic computation and then validated against circuit‐level simulations performed with 0.18 μm CMOS technology. Results demonstrate a strong agreement between theoretical and simulated data, with the amplifier achieving exceptional performance metrics: a DC gain of 122 dB, a gain‐bandwidth product (GBW) of 4.1 MHz, and a phase margin (PM) of 89°, while consuming less than 360 μW. Robustness is verified across process corners and through Monte Carlo analysis, confirming consistent performance under varying load capacitance and design parameters. Overall, this work presents an efficient and scalable compensation technique suitable for next‐generation analog and mixed‐signal applications.

In this paper, we present the development and characterization of a fully differential SiGe BiCMOS low noise amplifier (LNA) with active impedance matching for the readout of superconducting, quantum interference devices (SQUIDs). Impedance matching is particularly important when using the LNA over a broad frequency range and it is achieved using the Miller effect by adding a negative feedback loop. This approach avoids the degradation of the noise performance that is generated by simply using a parallel resistor at the LNA input. Furthermore, this impedance matching implementation preserves the signal to noise ratio (SNR) because both the signal and the noise are divided by 2 due to the negative feedback loop. This was verified by measuring a lower input voltage noise with the LNA input loaded with a 100  Ω resistor at 77 K compared to a short-circuit. In addition, we present simulations and measurements of the LNA frequency response, input impedance and input voltage noise. The obtained performances for the LNA show a flat gain of 173 V/V with a cut-off frequency of 26MHz and a referred input voltage white noise spectral density level of 0.34 nV/ Hz with a corner frequency of 72 Hz in input matching condition. These values are in good agreement with the simulations. Finally, a discussion about the impact of the impedance matching on the SQUID biasing is also presented.

This paper reviews recent developments in highly integrated all-digital frequency synthesizers suitable to deploy in low-power internet-of-things (IoT) applications. This review sets low power consumption as a key criterion for exploring the all-digital frequency synthesizer implemented in CMOS fabrication technology. The alignment with mainstream CMOS technology offers high-density, comprehensive, robust signal processing capability, making it very suitable for all-digital phase-locked loops to harvest that capacity, and it becomes inevitable. This review includes various divider-less low-power frequency synthesizers, including all-digital phase-locked loops (ADPLL), all-digital frequency-locked loops (ADFLL), and hybrid PLLs. This paper also discusses the latest architectural developments for ADPLLs to lead to low-power implementation, such as DTC-assisted TDC, embedded TDC, and various levels of hybridization in ADPLLs.