Explore the vast range of titles available.

To estimate 1-year prevalence and correlates of alcohol abuse, dependence, and subthreshold dependence (diagnostic orphans) among middle-aged and elderly persons in the United States. 2005–2007 National Surveys on Drug Use and Health. Sample included 10,015 respondents aged 50–64 years and 6,289 respondents older than 65 years. Data were analyzed by bivariate and multinomial regression analyses. Sociodemographic variables; alcohol use; Diagnostic and Statistical Manual of Mental Disorders, Fourth Edition abuse and dependence; major depression; nicotine dependence; illicit drug use; and nonmedical use of prescription drugs. Fifty-one percent of the sample used alcohol during the past year (56% in the 50–64 age group and 43% in the older than 65 age group). Overall, 11% (dependence 1.9%, abuse 2.3%, and subthreshold dependence 7.0%) of adults aged 50–64 and about 6.7% (dependence 0.6%, abuse 0.9%, and subthreshold dependence 5.2%) of those older than 65 reported alcohol abuse, dependence or dependence symptoms. Among past-year alcohol users, 20% (dependence 3.4%, abuse 4.0%, and subthreshold dependence 12.5%) of adults aged 50–64 and 15.4% (dependence 1.3%, abuse 2.1%, and subthreshold dependence 12.0%) of those older than 65 endorsed alcohol abuse or dependence symptoms. “Tolerance” (48%) and “time spent using” (37%) were the two symptoms most frequently endorsed by the subthreshold group. Compared with alcohol users without alcohol abuse or dependence symptoms, blacks or Hispanics and those who had nicotine dependence or used nonmedical prescription drugs had increased odds of subthreshold dependence. Diagnostic orphans also were more likely to engage in binge drinking than the asymptomatic group. Diagnostic orphans among middle-aged and elderly community adults show an elevated rate for binge drinking and nonmedical use of prescription drugs that require attention from healthcare providers.

The authors demonstrate a novel Charge-Plasma structure of Tunnel FET in which two different metal strips are implanted in oxide region to improve overall device’s performance. However, effect of temperature on the TFET is an important aspect to check the reliability of the device at different temperatures. So, a detailed study is done for the sensitivity of device toward temperature. Different parameters such as transfer characteristics, subthreshold slope (SS) and Threshold voltage ( V T ), whereas transconductance ( g m ), gate-to-drain capacitance ( C gd ), gate-to-source capacitance ( C gs ), intrinsic delay, transconductance generation factor (TGF), transconductance frequency product (TFP) and cutoff frequency ( f T ) are used as Analog/RF FOMs to carry out temperature analysis. Furthermore, the linearity parameters like gm2, VIP2, IMD3, gm3, VIP3 and IIP3 also show dependence on temperature which are studied in this work.

In this paper, analytical modeling of center channel potential has been performed for graded-channel gate-all-around (GC-GAA) junctionless field-effect transistor (JLFET). The three-dimensional (3D) Poisson’s equation has been solved to discover the center channel potential utilizing the parabolic approximation equation with excellent boundary conditions. The minimum center channel potential has been adopted to calculate the subthreshold current by the drift-diffusion method. The effect of high temperature and doping concentration on the center potential and subthreshold current has been investigated, and the results have been verified. The validity of the model has been verified using the ATLAS TCAD device simulator. The results reveal that the GC-GAA JLFET reduces the OFF-state leakage current with a high-graded abrupt junction inside the channel region. Hence, this finds many applications in low-power, high-speed, and high-density circuits.

This paper presents an L-structured gate TFET which analyses the concept of vertical tunneling by incorporating n + doped pocket. To ameliorate the device characteristics a wider tunnel junction area is facilitated as the channel direction remains perpendicular to the tunnel junction. Furthermore, to extricate the cumulated holes, gap has been introduced in the buried oxide layer eliminating the impact of kink. The pocket length and gap position of the design have been optimized to enhance the I ON /I OFF ratio. To exaggerate the ON current, the gate is designed in L-shaped enhancing the overlapping area of the gate over the channel. 54 mV/decade minimal subthreshold swing (SS) with enhanced current ratio of the order of 3.9 × 10 12 is achieved. Moreover, various RF parameters of the proposed device have been estimated by considering different range of temperature. Temperature dependency of various RF factors such as cut-off frequency (f T ), transconductance (g m ), gate capacitance (C GG ), transconductance frequency product (TFP) and intrinsic delay has been investigated in detail. The study of RF and DC parameters proves the proposed design to be a pertinent device for low power and high performance applications.

In this paper, a new structure for a silicon on insulator Schottky barrier MOSFET (SOI SB-MOSFET) has been proposed. The simulated device is calibrated with experimental result. Here n + pocket doping segregation in the source and drain side have been used. The simulated electrical characteristics of the proposed device With Source Extension (WSE) and With Source Drain Extension (WSDE) reveal more remarkable reduction in drain induced barrier tunneling (DIBT), high I on /I off and low Subthreshold swing(SS) than conventional device. Furthermore, the effect of varying temperature has been investigated on subthreshold swing for various oxide thickness (T ox ) and silicon film thickness (T Si ). Moreover, proposed SB-MOSFETs have been used in the inverter circuit, exhibit a high gain ( ˷ 12) and Noise Margin (NM H  = 0.4 and NM L  = 0.46).

In current article, an analytical model of a Triple-Material Dielectric-Pocket Gate-All-Around (TM-DP-GAA) MOSFET has been presented for elevated temperature conditions. The numerical model of surface potential has been developed for temperatures ranging from 300 to 700 K. The influence of temperature on the drain current, threshold voltage and subthreshold swing has been investigated. The performance of GAA MOSFET and TM-DP-GAA MOSFET has been compared for 30 nm channel length. The TM-DP-GAA MOSFET exhibits lower subthreshold swing, higher transconductance, high drain current and reduced leakage current in comparison to the other semiconductor devices. It has also been noticed that with increasing temperature, the variation in subthreshold current and subthreshold swing is minimal. The subthreshold swing improves by 12.42% over the DPGAA MOSFET. The dielectric pocket-based MOSFET is more resistant to temperature variation.The device simulation is performed using Silvaco TCAD.HighlightsTemperature variations can impact charge carrier mobility in semiconductors, which in turn affects the device's conductance.A device which shows minimal impact from temperature changes, maintain stable performance, Temperature changes can alter the DC parameters of the device, and observing these deviations precisely can improve device characteristics.By systematically changing the temperature, researchers can explore the thermal behaviour, making the device useful for low power applications.

This study presents the disorderedness effects on the subthreshold characteristics of atomically deposited ZnO thin-film transistors (TFTs). Bottom-gate ZnO TFTs show n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, degradable subthreshold swing. The charge-transport characteristics of the disordered semiconductor TFTs are severely affected by the localized trap states. Thus, we posit that the disorderedness factors, which are the interface trap capacitance and the diffusion coefficient of electrons, would result in the degradation. Considering the factors as gate-dependent power laws, we derive the subthreshold current–voltage relationship for disordered semiconductors. Notably, the gate-dependent disorderedness parameters are successfully deduced and consistent with those obtained by the gm/Ids method, which was for the FinFETs. In addition, temperature-dependent current–voltage analyses reveal that the gate-dependent interface traps limit the subthreshold conduction, leading to the diffusion current. Thus, we conclude that the disorderedness factors of the ZnO films lead to the indefinable subthreshold swing of the ZnO TFTs.

Aggressive technology scaling has inevitably led to reliability becomes a major concern for modern high-speed and high-performance integrated circuits. The major reliability concerns in nanoscale very-large-scale integration design are the time-dependent negative bias temperature instability (NBTI) degradation. Owing to increasing vertical oxide field and higher operating temperature, the threshold voltage of P-channel MOS transistors increases with time under NBTI. This study presents a novel subthreshold Darlington pair-based NBTI degradation sensor under the stress conditions. The proposed sensor provides the high degree of linearity and sensitivity under subthreshold conditions. The Darlington pair used in the circuit provides the stability and the high-input impedance of the circuit makes it less affected by the process variations. Owing to high sensitivity, the proposed sensor is best suited for sensing of temperature variation, process variation, and temporal degradation during measurement. The sensitivity of the proposed sensor at room temperature is 0.239 mV/nA under subthreshold conditions. The proposed sensor is less affected by the process variation and has the maximum deviation of 0.0011 mV at standby leakage current of 30 nA.

The remarkable development and continual proliferation of research in the nanotechnology field have led to improvement in the efficiency of elementary devices. To improve their performance, the parameters of such devices can be scaled down while optimizing their characteristics. However, this simultaneously results in degraded switching characteristics and the appearance of short-channel effects. Multigate-based fin-shaped field-effect transistors (FinFETs) represent a new option to address all these problems. However, thermal failure of FinFET devices under nominal operating conditions is an important issue in the design and implementation of high-speed semiconductor devices. It is also seen that bulk FinFETs exhibit better thermal performance compared with silicon-on-insulator FinFETs. In the work presented herein, various FinFET characteristics including the subthreshold swing, drain-induced barrier lowering, threshold voltage, and drain current were investigated as functions of temperature. The (effective) channel length is larger than the physical gate length (in off-state) due to the undoped underlap regions. This paper also discusses the effects of drain, source, and gate overlap.

An analytical threshold voltage model for MOSFETs has been developed using different gate dielectric oxides by using MATLAB software. This paper explains the dependency of threshold voltage on the dielectric material. The variation in the subthreshold currents with the change in the threshold voltage sue to the change of dielectric material has also been studied.