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During deep and ultra-deep well drilling operations, the throttling performance of the hydraulic-while-drilling jar is significantly affected by the combined influence of temperature-induced differential thermal expansion among components and changes in the rheological properties of hydraulic oil. These effects often lead to unstable jarring behavior or even complete failure to trigger jarring during stuck pipe events. Here, we propose a high-temperature degradation evaluation model for the throttling performance of the throttle valve in an HWD jar based on thermal expansion testing of individual components and high-temperature rheological experiments of hydraulic oil. By using the variation characteristics of the throttling passage geometry as a linkage, this model integrates the thermo-mechanical coupling of the valve body with flow field simulation. Numerical results reveal that fluid pressure decreases progressively along the flow path through the throttle valve, while flow velocity increases sharply at the channel entrance and exhibits mild fluctuations within the throttling region. Under fluid compression, the throttling areas of both the upper and lower valves expand to some extent, with their spatial distributions closely following the pressure gradient and decreasing gradually along the flow direction. Compared with ambient conditions, thermal expansion under elevated temperatures causes a more pronounced increase in throttling area. Additionally, as hydraulic oil viscosity decreases with increasing temperature, flow velocities and mass flow rates rise significantly, leading to a marked deterioration in the throttling performance of the drilling jar under high-temperature downhole conditions.

The throttling performance of conventional throttle orifice structures of fluid control valves is very low. Therefore, this paper proposes a novel trapezoidal throttle orifice with excellent throttling performance. The effect of the taper of the throttle orifice on the erosion was researched. Firstly, two schemes of trapezoidal throttle orifice were proposed according to the fluid control valve. Secondly, the excellent throttling performance of the trapezoidal throttle orifice was compared and optimized. Finally, a numerical simulation method of the erosion-resistant ability of the trapezoidal throttle orifice was established. It was found that for the same throttling area, the differential pressure of the trapezoidal orifice was higher than that of the conventional rectangular orifice by about 18.6%. The taper had little effect on the gas production, which increased by only 3.3% during the 10° to 30° change. The maximum erosion was firstly reduced and then increased with increases in the angle from 0 to 25°of the taper. Moreover, the minimum was achieved at about a 20° taper angle. The above research methods provide a theoretical basis for optimizing the size and structure of orifices and the sealing reliability of fluid control valves.

Pump-controlled hydraulic circuits are more efficient than conventional valve-controlled ones. Pump-controlled hydraulic circuits for double rod cylinders are well developed and, presently, implemented in many applications including aviation. Nevertheless, current pump-controlled hydraulic circuits for single-rod cylinders encounter performance issues during specific operating conditions. Pressure and actuator velocity oscillations are encountered when operating in this critical zone. Different concepts, techniques and designs are proposed by researchers to overcome such vibration issues. In this research, three different concepts to overcome the reported oscillation problem in these circuits are presented; namely: (1) shifting of critical zone into lower loading ranges, (2) applying selective leakage, and (3) applying selective throttling. Simulation studies indicated that the new concepts alleviated the oscillation issue of the common pump-controlled circuits, and improved their performances. The second and third concepts, in particular, were capable of eliminating the whole critical zone. The first concept reduced the area of the critical zone in the load-velocity plane and lessened undesirable effect of oscillations. Simulation studies further proved the enhanced performance of circuits that applies these concepts as compared to previously-designed circuits.

Three‐dimensional networks‐on‐chip are beneficial for performance improvement, but suffer from severe thermal issues. Dynamic thermal management (DTM) schemes have been proposed to keep the temperature below the thermal limit while improve the system performance. However, existing fully‐throttling DTM schemes degrade the network availability and thus decrease the system performance. In this study, a novel collaborative fuzzy‐based partially‐throttling DTM (CFP‐DTM) scheme is developed. Two main components are involved in the CFP‐DTM: (i) a fuzzy‐based clock gating scheme dynamically adjusting the throttling ratio and throttled nodes (ii) a highly adaptive throttling‐aware routing scheme for packets to detour the easily congested channels. Experiments show that, compared with the fully‐throttling based vertical throttling scheme, the proposed CFP‐DTM can improve the throughput by 27.5% and reduce the thermal control oscillation by 3°C under the maximum system workload.

Many application scenarios of edge visual inference, e.g., robotics or environmental monitoring, eventually require long periods of continuous operation. In such periods, the processor temperature plays a critical role to keep a prescribed frame rate. Particularly, the heavy computational load of convolutional neural networks (CNNs) may lead to thermal throttling and hence performance degradation in few seconds. In this paper, we report and analyze the long-term performance of 80 different cases resulting from running five CNN models on four software frameworks and two operating systems without and with active cooling. This comprehensive study was conducted on a low-cost edge platform, namely Raspberry Pi 4B (RPi4B), under stable indoor conditions. The results show that hysteresis-based active cooling prevented thermal throttling in all cases, thereby improving the throughput up to approximately 90% versus no cooling. Interestingly, the range of fan usage during active cooling varied from 33% to 65%. Given the impact of the fan on the power consumption of the system as a whole, these results stress the importance of a suitable selection of CNN model and software components. To assess the performance in outdoor applications, we integrated an external temperature sensor with the RPi4B and conducted a set of experiments with no active cooling in a wide interval of ambient temperature, ranging from 22 °C to 36 °C. Variations up to 27.7% were measured with respect to the maximum throughput achieved in that interval. This demonstrates that ambient temperature is a critical parameter in case active cooling cannot be applied.

Unified virtual memory was introduced in modern GPUs to enable a new programming model for programmers. This method manages memory pages between the GPU and CPU automatically, reducing the complexity of data management for programmers. However, when a GPU programs generates a large memory footprint that exceeds the GPU memory capacity, thrashing can occur, leading to significant performance degradation. To address this issue, this paper proposes a thread throttling that restricts the active thread groups, thereby alleviating memory oversubscription and improving performance. The proposed method adjusts the active thread group at compile time to ensure that their memory footprints fit within the available memory capacity. The effectiveness of the proposed method was evaluated using GPU programs that experience memory oversubscription. The results showed that our approach improved the performance of the original programs by 3.44 × on average. This represents a 1.53 × performance improvement compared to static thread throttling.

GPUs are becoming more and more appealing targets for side-channel attacks because of their high levels of parallelism and shared hardware resources. In order to reduce side-channel assaults on GPUs, we provide a unique dynamic shader termination and throttling approach in this research. The main concept is to use runtime profiling and heuristics to dynamically terminate and restrict the frequency and concurrency of shader programs. We use the open-source GPGPU simulator GPUOwl to implement the suggested method. Our findings show that the suggested method may successfully thwart a variety of side-channel assaults while having no influence on efficiency. Over a range of benchmarks, the average overhead introduced by the dynamic shader termination and throttling is 5.6%. At the same time, it successfully thwarts recently demonstrated cache-based and timing-based side-channel attacks on GPUs. Thus, the proposed technique offers an efficient software-based defence to enhance the side-channel security of GPUs.

Dynamic thermal management (DTM) techniques of three‐dimensional (3D) Network‐on‐Chips (NoCs) are employed to rescue the chip from thermal difficulties. Reactive routing algorithms, which utilise router throttling technique as a popular DTM, disregard distribution of heat generation of routers resulting in more throttled routers as well as long packet delays in throttled processing elements. This study proposes a reactive routing algorithm for 3D NoCs to (i) dynamically detour packets from hot zones containing throttled routers and (ii) minimise the number of required router throttling in the network. The proposed routing algorithm defines two virtual networks to enhance the path diversity for packets in each layer of 3D NoCs. The selection of diverse paths distributes heat generation to alleviate the thermal variance. The proposed routing algorithm is analysed by turn model to achieve deadlock freedom. Access Noxim simulator is also used to evaluate the performance and the thermal behaviour of the proposed routing algorithm in the variety of conditions. Results show that the proposed routing algorithm improves temperature variance by 9–39% and reduces number of throttled routers by 16–86%, which is achieved at the cost of one extra virtual channel per each physical channel in the XY‐plane.

Aerospike nozzles represent an interesting solution for Single-Stage-To-Orbit or clustered launchers owing to their self-adapting capability, which can lead to better performance compared to classical nozzles. Furthermore, they can provide thrust vectoring in several ways. A simple solution consists of applying differential throttling when multiple combustion chambers are used. An alternative solution is represented by fluidic thrust vectoring, which requires the injection of a secondary flow from a slot. In this work, the flow field in a linear aerospike nozzle was investigated numerically and both differential throttling and fluidic thrust vectoring were studied. The flow field was predicted by solving the Reynolds-averaged Navier–Stokes equations. The thrust vectoring performance was evaluated in terms of side force generation and axial force reduction. The effectiveness of fluidic thrust vectoring was investigated by changing the mass flow rate of secondary flow and injection location. The results show that the response of the system can be non-monotone with respect to the mass flow rate of the secondary injection. In contrast, differential throttling provides a linear behaviour but it can only be applied to configurations with multiple combustion chambers. Finally, the effects of different plug truncation levels are discussed.

In today’s multiprocessor systems-on-a-chip, the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time analysis. Memory regulation via throttling is one of the most practical techniques to mitigate interference. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and conduct an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite.