Explore the vast range of titles available.

With the advancement in CMOS technology and multiple processors on the chip, communication across these cores is managed by a network-on-chip (NoC). Power and performance of these NoC interconnects have become a significant factor.The authors aim to reduce the leakage power consumption of NoC buffers by the use of non-volatile spin transfer torque random access memory (STT-RAM)-based buffers. STT-RAM technology has the advantages of high density and low leakage but suffers from low endurance. This low endurance has an impact on the lifetime of the router on the whole due to unwanted write-variations governed by virtual channel (VC) allocation policies. Here various VC allocation policies that help the uniform distribution of the writes across the buffers are proposed. Iso-capacity and iso-area-based alternatives to replace SRAM buffers with STT-RAM buffers are also presented. Pure STT-RAM buffers, however, impact the network latency. To mitigate this, a hybrid variant of the proposed policies which uses alternative VCs made of SRAM technology in the case of heavy network traffic is proposed. Experimental evaluation of full system simulation shows that proposed policies reduce the write variation by 99% and improve lifetime by 3.2 times and 1093 times, respectively. Also a 55.5% gain in the energy delay product is obtained.

The need for power-efficient devices, such as smart sensor nodes, mobile devices, and portable digital gadgets, is markedly increasing and these devices are becoming commonly used in daily life. These devices continue to demand an energy-efficient cache memory designed on Static Random-Access Memory (SRAM) with enhanced speed, performance, and stability to perform on-chip data processing and faster computations. This paper presents an energy-efficient and variability-resilient 11T (E2VR11T) SRAM cell, which is designed with a novel Data-Aware Read–Write Assist (DARWA) technique. The E2VR11T cell comprises 11 transistors and operates with single-ended read and dynamic differential write circuits. The simulated results in a 45 nm CMOS technology exhibit 71.63% and 58.77% lower read energy than ST9T and LP10T and lower write energies of 28.25% and 51.79% against S8T and LP10T cells, respectively. The leakage power is reduced by 56.32% and 40.90% compared to ST9T and LP10T cells. The read static noise margin (RSNM) is improved by 1.94× and 0.18×, while the write noise margin (WNM) is improved by 19.57% and 8.70% against C6T and S8T cells. The variability investigation using the Monte Carlo simulation on 5000 samples highly validates the robustness and variability resilience of the proposed cell. The improved overall performance of the proposed E2VR11T cell makes it suitable for low-power applications.

Cache memory is a key component for most microprocessors in embedded system. The increasing processing load has resulted in an upsurge in the demand for low power, high performance SRAM bit cells. Consequently, in this paper a 7T bit cell is designed for feature size 32 nm and 300 mV supply voltage. The improvement in the performance of the proposed cell is validated against the results obtained for pre-existing 6T, 7T, 8T, 9T, and 10T cells. The read and hold noise margin for the cell is obtained to be 96 and 68 mV respectively, whereas the static margin for the write operation is 170 mV. To perform a successful write operation, a pulse-width of 30 ns is utilized. The power analysis reveals that the proposed cell has minimal read/write power consumption. The leakage power for the cell is 8.4 pW and 1.2 pW for Q = ‘0’ and ‘1’ respectively. Tolerance analysis justifies that the cell maintains its functionality and yields credible outputs under process-voltage-temperature variations for static performance metrics. The layout for the proposed 7T cell occupies 0.584 µm 2 area. This is 5.55% smaller than a single ended 6T. The area for other 7T counterparts, 8T, 9T, and 10T cells is larger than the proposed cell.

The use of Internet of Things (IoT) applications become dominant in many systems. Its on-chip data processing and computations are also increasing consistently. The battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT applications. The cache memory designed on Static Random-Access Memory (SRAM) cell with features such as low power, high speed, and process tolerance are highly important for the IoT memory system. Therefore, a process tolerant SRAM cell with low power, improved delay and better stability is presented in this research paper. The proposed cell comprises 11 transistors designed with symmetric approach for write operations and single ended circuit for read operations that exhibits an average dynamic power saving of 43.55% and 47.75% for write and 35.59% and 36.56% for read operations compared to 6 T and 8 T SRAM cells. The cell shows an improved write delay of 26.46% and 37.16% over 6 T and 8 T and read delay is lowered by 50.64% and 72.90% against 6 T and 10 T cells. The symmetric design used in core latch to improve the write noise margin (WNM) by 17.78% and 6.67% whereas the single ended separate read circuit improves the Read Static Noise Margin (RSNM) by 1.88x and 0.33x compared to 6 T and 8 T cells. The read power delay product and write power delay product are lower by 1.94x, 1.39x and 0.17x, 2.02x than 6 T and 8 T cells respectively. The lower variability from 5000 samples validates the robustness of the proposed cell. The simulations are carried out in Cadence virtuoso simulator tool with Generic Process Design Kit (GPDK) 45 nm technology file in this work.

This chapter contains sections titled: Poirot Miss Marple Thrillers

Chapter 3 is a tutorial on optical lithography which encompasses the physics and theory of operation including issues associated with advanced processes, and corresponding solutions. It begins with a brief historical perspective, an introduction and simple imaging theory. Then it takes the reader through the challenges for the 100 nm nodes and beyond. This is followed by an overview of the significant process variations, the impact of low‐κ imaging on process sensitivities. A detailed discussion of low‐κ imaging follows, including its effect on depth of focus; exposure tolerance; mask error factor; sensitivity to aberrations; CD variation as a function of pitch; and corner rounding radius. The next topic covered is the state of the art resolution enhancement techniques which will extend the resolution of the current lithography down to a quarter of the wave‐length of the illumination used. This is followed by a discussion of the Physical Design Style Impact on RET and OPC Complexity. The chapter concludes with a look ahead into the future Lithography Technologies—the evolutionary as well as the revolutionary road maps.