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Under a foggy environment, the air contains a large number of suspended particles, which lead to the loss of image information and decline of contrast collected by the vision system. This makes subsequent processing and analysis difficult. At the same time, the current stage of the defogging system has problems such as high hardware cost and poor real-time processing. In this article, an image defogging system is designed based on the ZYNQ platform. First of all, on the basis of the traditional dark-channel defogging algorithm, an algorithm for segmenting the sky is proposed, and in this way, the image distortion caused by the sky region is avoided, and the atmospheric light value and transmittance are estimated more accurately. Then color balancing is performed after image defogging to improve the quality of the final output image. The parallel computing advantage and logic resources of the PL (Programmable Logic) part (FPGA) of ZYNQ are fully utilized through instruction constraints and logic optimization. Finally, the visible light detector is used as the input to build a real-time video processing experiment platform. The experimental results show that the system has a good defogging effect and meet the real-time requirements.

Polarization navigation is an emerging navigation technology, that exhibits significant advantages, including strong anti-interference capability and non-cumulative errors over time, making it highly promising for applications in aerospace, autonomous driving, and robotics. To address the requirements of high integration and low power consumption for tri-directional polarization navigation sensors, this study proposes a system-on-chip (SoC) design solution. The system employs the ZYNQ MPSoC (Xilinx Inc., San Jose, CA, USA) as its core, leveraging hardware acceleration on the Programmable Logic (PL) side for three-angle polarization image data acquisition, image preprocessing, and edge detection. Simultaneously, the Processing System (PS) side orchestrates task coordination, performs polarization angle resolution, and extracts the solar meridian via Hough transform. Experimental results demonstrate that the system achieves an average heading angle output time interval of 9.43 milliseconds (ms) with a mean error of 0.50°, fulfilling the real-time processing demands of mobile devices.

The prominence of image processing in today’s cutting-edge technology is undeniable. Integrating software with hardware leverages both strengths, resulting in a real-time processing system that is efficient and streamlined. Raw images are usually affected by noise, which hinders the acquisition of good-quality and detailed images; hence, denoising becomes necessary. This paper proposes a modified min-max median (MMM) filter to remove impulse noise and a Tritonic sorter to localize corrupted pixels. The proposed denoising method focuses on localizing noisy pixels, unlike traditional denoising approaches, which focus only on noise detection and filtering. A min-max sheet provides the location of the corrupted pixels, and filtering is performed on them. The Tritonic Sorter, consisting of a max locator and a min locator, compares three input values and finds the minimum, maximum and median values among them. Compared to other state-of-the-art methods, the proposed method minimizes the number of comparators needed to carry out the sorting process. The proposed method was synthesized in the ZedBoard Zynq kit using the Vivado tool. The results show that the area improved by 27%, and the power improved by 16.23% compared with those of the existing method.

When a CMOS (Complementary Metal–Oxide–Semiconductor) imaging system operates at a high frame rate or a high line rate, the exposure time of the imaging system is limited, and the acquired image data will be dark, with a low signal-to-noise ratio and unsatisfactory sharpness. Therefore, in order to improve the visibility and signal-to-noise ratio of remote sensing images based on CMOS imaging systems, this paper proposes a low-light remote sensing image enhancement method and a corresponding ZYNQ (Zynq-7000 All Programmable SoC) design scheme called the BGIR (Bilateral-Guided Image Restoration) algorithm, which uses an improved multi-scale Retinex algorithm in the HSV (hue–saturation–value) color space. First, the RGB image is used to separate the original image’s H, S, and V components. Then, the V component is processed using the improved algorithm based on bilateral filtering. The image is then adjusted using the gamma correction algorithm to make preliminary adjustments to the brightness and contrast of the whole image, and the S component is processed using segmented linear enhancement to obtain the base layer. The algorithm is also deployed to ZYNQ using ARM + FPGA software synergy, reasonably allocating each algorithm module and accelerating the algorithm by using a lookup table and constructing a pipeline. The experimental results show that the proposed method improves processing speed by nearly 30 times while maintaining the recovery effect, which has the advantages of fast processing speed, miniaturization, embeddability, and portability. Following the end-to-end deployment, the processing speeds for resolutions of 640 × 480 and 1280 × 720 are shown to reach 80 fps and 30 fps, respectively, thereby satisfying the performance requirements of the imaging system.

With the advent of the information age, the effective identification of sensitive information and the leakage of sensitive information during the transmission process are becoming increasingly serious issues. We designed a sensitive information recognition and encryption transmission system based on a decision tree. By training sensitive data to build a decision tree, unknown data can be classified and identified. The identified sensitive information can be marked and encrypted to achieve intelligent recognition and protection of sensitive information. This lays the foundation for the development of an information recognition and encryption transmission system.

Speech recognition has progressed tremendously in the area of artificial intelligence (AI). However, the performance of the real-time offline Chinese speech recognition neural network accelerator for edge AI needs to be improved. This paper proposes a configurable convolutional neural network accelerator based on a lightweight speech recognition model, which can dramatically reduce hardware resource consumption while guaranteeing an acceptable error rate. For convolutional layers, the weights are binarized to reduce the number of model parameters and improve computational and storage efficiency. A multichannel shared computation (MCSC) architecture is proposed to maximize the reuse of weight and feature map data. The binary weight-sharing processing engine (PE) is designed to avoid limiting the number of multipliers. A custom instruction set is established according to the variable length of voice input to configure parameters for adapting to different network structures. Finally, the ping-pong storage method is used when the feature map is an input. We implemented this accelerator on Xilinx ZYNQ XC7Z035 under the working frequency of 150 MHz. The processing time for 2.24 s and 8 s of speech was 69.8 ms and 189.51 ms, respectively, and the convolution performance reached 35.66 GOPS/W. Compared with other computing platforms, accelerators perform better in terms of energy efficiency, power consumption and hardware resource consumption.

The Antarctic region holds significant scientific research value and potential resources. Currently, limited research exists on the use of seismic exploration methods for Antarctic subglacial lakes compared to their use on other continents. Moreover, few reports are available on systems capable of multi-channel seismic data acquisition, remote data quality monitoring, and high-speed real-time data recycling in the extremely low temperatures of Antarctica. In this study, we developed a Zynq-based seismic acquisition station for polar exploration. The system features a compact design, lightweight construction, high data collection accuracy, excellent cold resistance, low power consumption, and real-time control. The software and hardware design of the system are described here, and validity testing is presented. The main controller utilizes a Zynq series system-on-chip integrated with an FPGA (Field-Programmable Gate Array) and an ARM (Advanced RISC Machine), enabling functions such as local data storage on a secure digital card, Wi-Fi wireless human–machine interaction, and high-speed Ethernet data transmission. Furthermore, to enhance data acquisition accuracy under low-temperature conditions, a neural network was employed for the temperature drift correction of the analog-to-digital converter chip. The validity test results showed that the station operated stably, was easy to use, and met the high-standard requirements for polar exploration.

With the rapid development of artificial intelligence technology, optimizing the convolutional operation of convolutional neural network (hereinafter referred to as CNN) to adapt to the resource constraints of embedded systems has become one of the current research hotspots. In this paper, we explain the basic connotation of CNN and embedded platform Zynq, and optimize the Im2col-Gemm algorithm based on Darknet framework, so as to further optimize the CNN model. The CNN before and after optimization under different hardware configurations are compared through acceleration tests, and the average time spent on each layer and the total time of CNN operations are recorded, which clearly concludes that the Zynq combining the optimized CNN can achieve 658.12 and 23.18 times acceleration with respect to CPU and GPU, respectively. Through the character recognition detection and traffic sign detection, Zynq’s character recognition with optimized CNN achieves 220FPS with less than 4.5W power consumption, and it only takes about 4.5ms to recognize a picture. Meanwhile, the traffic sign recognition has a high recognition rate of 97.8% on average and a low leakage rate of 8.28%, which verifies that Zynq with optimized CNN is fast and consumes low power, which is advantageous for applications in real-time image processing. Optimizing CNN based on embedded systems helps promote the continuous upgrading of artificial intelligence.

The estimation of human hand pose has become the basis for many vital applications where the user depends mainly on the hand pose as a system input. Virtual reality (VR) headset, shadow dexterous hand and in-air signature verification are a few examples of applications that require to track the hand movements in real-time. The state-of-the-art 3D hand pose estimation methods are based on the Convolutional Neural Network (CNN). These methods are implemented on Graphics Processing Units (GPUs) mainly due to their extensive computational requirements. However, GPUs are not suitable for the practical application scenarios, where the low power consumption is crucial. Furthermore, the difficulty of embedding a bulky GPU into a small device prevents the portability of such applications on mobile devices. The goal of this work is to provide an energy efficient solution for an existing depth camera based hand pose estimation algorithm. First, we compress the deep neural network model by applying the dynamic quantization techniques on different layers to achieve maximum compression without compromising accuracy. Afterwards, we design a custom hardware architecture. For our device we selected the FPGA as a target platform because FPGAs provide high energy efficiency and can be integrated in portable devices. Our solution implemented on Xilinx UltraScale+ MPSoC FPGA is 4.2× faster and 577.3× more energy efficient than the original implementation of the hand pose estimation algorithm on NVIDIA GeForce GTX 1070.

Convolutional Neural Networks (CNNs) are becoming increasingly popular in deep learning applications, e.g. image classification, speech recognition, medicine, to name a few. However, the CNN inference is computationally intensive and demanding a large among of memory resources. In this work is proposed a CNN inference hardware accelerator, which was implemented in a co-processing scheme. The aim is to reduce the hardware resources and achieve the better possible throughput. The design was implemented in the Digilent Arty Z7-20 development board, which is based on System on Chip (SoC) Zynq-7000 of Xilinx. Our implementation achieved a  of accuracy for the MNIST database using only 12-bits fixed-point format. The results show that the co-processing scheme operating at a conservative speed of 100 MHz can identify around 441 images per second, which is about 17% times faster than a 650 MHz - software implementation. It is difficult to compare our results against other implementations based on Field-Programmable Gate Array (FPGA), because the others implementations are not exactly like ours. However, some comparisons, regarding the logical resources used and accuracy, suggest that our work could be better than previous works.