Paper

Adiabatic Capacitive Neuron: An Energy-Efficient Functional Unit for Artificial Neural Networks

Prodromakis, Themis, Maheshwari, Sachin, Himadri Singh Raghav, Smart, Mike, Serb, Alexander

2026

Overview

This paper introduces a new, highly energy-efficient, Adiabatic Capacitive Neuron (ACN) hardware implementation of an Artificial Neuron (AN) with improved functionality, accuracy, robustness and scalability over previous work. The paper describes the implementation of a 12-bit single neuron, with positive and negative weight support, in an \\(0.18 m\\) CMOS technology. The paper also presents a new Threshold Logic (TL) design for a binary AN activation function that generates a low symmetrical offset across three process corners and five temperatures between \\(-55^o\\)C and \\(125^o\\)C. Post-layout simulations demonstrate a maximum rising and falling offset voltage of 9\\(mV\\) compared to conventional TL, which has rising and falling offset voltages of 27\\(mV\\) and 5\\(mV\\) respectively, across temperature and process. Moreover, the proposed TL design shows a decrease in average energy of 1.5\\(\\%\\) at the SS corner and 2.3\\(\\%\\) at FF corner compared to the conventional TL design. The total synapse energy saving for the proposed ACN was above 90\\(\\%\\) (over 12x improvement) when compared to a non-adiabatic CMOS Capacitive Neuron (CCN) benchmark for a frequency ranging from 500\\(kHz\\) to 100\\(MHz\\). A 1000-sample Monte Carlo simulation including process variation and mismatch confirms the worst-case energy savings of \\(\\>\\)90\\(\\%\\) compared to CCN in the synapse energy profile. Finally, the impact of supply voltage scaling shows consistent energy savings of above 90\\(\\%\\) (except all zero inputs) without loss of functionality.

• Publisher: Cornell University Library, arXiv.org
• Subject: Adiabatic flow / Artificial neural networks / CMOS / Electric potential / Monte Carlo simulation / Threshold logic / Voltage