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Development and Validation of an optimized syndromes block for reed solomon decoder
by
Anas El Habti, El Idrissi
, Omar, Mouhib
, Azeddine, Wahbi
, Mohamed, Elghayyaty
, Hadjoudja, Abdelkader
in
Algorithms
/ Data transmission
/ Decoding
/ Digital Video Broadcasting
/ Disorders
/ dvb-t and dvb-s2 transmission chains
/ Energy consumption
/ fpga
/ galois field
/ Hardware description languages
/ rs codes
/ Symbols
/ syndrome block. vhdl
/ Video transmission
2023
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Development and Validation of an optimized syndromes block for reed solomon decoder
by
Anas El Habti, El Idrissi
, Omar, Mouhib
, Azeddine, Wahbi
, Mohamed, Elghayyaty
, Hadjoudja, Abdelkader
in
Algorithms
/ Data transmission
/ Decoding
/ Digital Video Broadcasting
/ Disorders
/ dvb-t and dvb-s2 transmission chains
/ Energy consumption
/ fpga
/ galois field
/ Hardware description languages
/ rs codes
/ Symbols
/ syndrome block. vhdl
/ Video transmission
2023
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Development and Validation of an optimized syndromes block for reed solomon decoder
by
Anas El Habti, El Idrissi
, Omar, Mouhib
, Azeddine, Wahbi
, Mohamed, Elghayyaty
, Hadjoudja, Abdelkader
in
Algorithms
/ Data transmission
/ Decoding
/ Digital Video Broadcasting
/ Disorders
/ dvb-t and dvb-s2 transmission chains
/ Energy consumption
/ fpga
/ galois field
/ Hardware description languages
/ rs codes
/ Symbols
/ syndrome block. vhdl
/ Video transmission
2023
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Development and Validation of an optimized syndromes block for reed solomon decoder
Journal Article
Development and Validation of an optimized syndromes block for reed solomon decoder
2023
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Overview
Reed Solomon decoder plays an indispensable role in many applications involving data transmission, storage applications and Video broadcasting DVB-T and DVB-S2. In this work we propose a new optimized parallel syndrome block [67] for the Reed Solomon RS code (15,11) used in digital Video broadcasting DVB-T. Therefore, this proposed parallel block is compared to the serial syndrome block existing. On the basis of this technique a new architecture based on three syndromes in parallel is developed. This technique reduces both the energy consumption and the number of iterations. The RS code (15, 11) is composed of 255 symbols that are multiples of 3. The symbols are entered in parallel in the syndrome block. These decoding algorithms developed in this work are compared with the existing algorithms, and they are evaluated through a simulation using the hardware description language VHDL, then they are implemented on a Xilinx Spartan type FPGA card using the XILINX software.
Publisher
EDP Sciences
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