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A Novel and Voltage Resilient Design of Ultra-High-Speed Low Power Keeper Based Full Adder
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A Novel and Voltage Resilient Design of Ultra-High-Speed Low Power Keeper Based Full Adder
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Journal Article
A Novel and Voltage Resilient Design of Ultra-High-Speed Low Power Keeper Based Full Adder
2024
Overview
This research article introduces an innovative 1-bit full adder design, leveraging grounded keeper circuitry. To implement full adder, keeper based XOR-XNOR cell -based design approach is used. Achieving full swing output voltage is one of the critical challenges in the designing of full adder. In this paper 8-T XOR-XNOR cell is proposed and simulated using HSPICE software at 90 nm technology node. The introduction of keeper circuit, which decreases propagation delay and offer full output voltage swing, is the primary focus of this research. Furthermore, this work puts forth an original design for a voltage-resilient ultra high-speed low-power keeper-based 1-bit full adder (UHSLPFA). Our research delves into a comprehensive comparison of various full adder designs, focusing on power dissipation (PWR), propagation delay (tp), and power-delay product (PDP). Notably, our proposed 20-T full adder design boasts notably reduced propagation delay and power consumption when compared to the existing counterparts. The envisioned application scope for this voltage-resilient ultra-high-speed-low-power keeper-based 1-bit full adder extends to the development of arithmetic logic units, multipliers, calculators, and graphical processing units. To gauge its voltage resilience, our proposed UHSLPFA is subjected to simulation across a range of supply voltages, from 0.6 to 1.5 V. This evaluation uncovers variations in PWR, tp, and PDP, showcasing the superior resilience of our design compared to contemporary state-of-the-art alternatives. The performance of the proposed full adder is also evaluated in 4-bit ripple carry adder.
Publisher
Springer US,Springer Nature B.V
Subject
