Journal Article

A 7‐Bit 700 MS/s 2b/Cycle Asynchronous SAR ADC With Partially Merged Capacitor Switching

Ahn, Gil‐Cho, Kwak, Myoungbo, Park, Jaewoo, Kim, Hyoung‐Jung, Park, Seung‐Hun, Choi, Young, Lee, Jae‐Hyuk, Lim, Jae‐Geun, Boo, Jun‐Ho, Park, Seong‐Bo

2025

Overview

This letter introduces a 7‐bit, 700 MS/s, 2b/cycle asynchronous successive approximation register (SAR) analogue‐to‐digital converter (ADC). To relax the settling requirement, the capacitive digital‐to‐analogue converter (CDAC) is designed with non‐binary weighting to provide redundancy, implemented using a pre‐charge reduction scheme that removes next‐cycle pre‐charge activity in a 2b/cycle SAR ADC. To reduce the area of this non‐binary weighted CDAC, a partially merged capacitor switching scheme is proposed. The prototype ADC is fabricated in a 28 nm CMOS process with an active die area of 0.0077 mm2. At a 700 MS/s sampling rate, the ADC achieves a signal‐to‐noise‐and‐distortion ratio of 37.6 dB and a spurious‐free dynamic range of 49.1 dB at the Nyquist input frequency. The power consumption is 2.41 mW from a 1.0 V supply, resulting in a Walden figure of merit of 55.56 fJ/conversion step at Nyquist. This letter presents a 7‐bit asynchronous successive approximation register analogue‐to‐digital converter operating at 700 MS/s with a 2b/cycle conversion scheme, incorporating a partially merged capacitor switching (PMCS). By applying PMCS to the non‐binary weighted capacitive digital‐to‐analogue converter (CDAC), the number of unit capacitors is effectively reduced, contributing to a smaller CDAC area.

• Subject: analogue circuits / analogue–digital conversion / CMOS analogue integrated circuits / high‐speed integrated circuits / switched capacitor networks