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A Dual-Mode Adaptive Bandwidth PLL for Improved Lock Performance
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A Dual-Mode Adaptive Bandwidth PLL for Improved Lock Performance
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Journal Article
A Dual-Mode Adaptive Bandwidth PLL for Improved Lock Performance
2025
Overview
This paper proposed an adaptive bandwidth Phase-Locked Loop (PLL) that integrates integer-N and fractional-N switching for energy-efficient RF synthesis in IoT and mobile applications. The architecture exploits wide-bandwidth integer-N mode for rapid lock acquisition, then seamlessly transitions to narrow-bandwidth fractional-N mode for high-resolution synthesis and noise optimization. The architecture features a bandwidth-reconfigurable loop filter with intelligent switching control that monitors phase error dynamics. A novel adaptive digital noise filter mitigates ΔΣ quantization noise, replacing conventional synchronous delay lines. The multi-loop structure incorporates a high-resolution digital phase detector to enhance frequency accuracy and minimize jitter across both operating modes. With 180 nm CMOS technology, the PLL consumes 13.2 mW, while achieving −119 dBc/Hz in-band phase noise and 1 psrms integrated jitter. With an operating frequency range at 2.9–3.2 GHz from a 1.8 V supply, the circuit achieves a worst case fractional spur of −62.7 dBc, which corresponds to a figure of merit (FOM) of −228.8 dB. Lock time improvements of 70% are demonstrated compared to single-mode implementations, making it suitable for high-precision, low-power wireless communication systems requiring agile frequency synthesis.
Publisher
MDPI AG
