Journal Article

Efficient Multiple 4-Bit ALU Designs for Fast Computation and Reduced Area

El-Bendary, Mohsen A. M, Ayman, M

2022

Overview

In this work, an efficient full-swing (FS)-gate diffusion input (GDI) logic style is used for implementing full adder (FA) and arithmetic logic unit (ALU) circuits. The performance of the ALU in delay time, power consumption, and area terms is strongly dependent on the performance efficiency of the FA circuits utilized in its construction. In this research paper, multi-efficient power and high-speed ALU circuits are proposed with outputs in full-swing form and improved area. The proposed circuit is evaluated and tested using the Cadence Virtuoso simulation package in the 65 nm CMOS process. The proposed ALUs reduce power consumption by 20.01% and 4% compared with the ALU implemented by the traditional CMOS technique and GDI-based unit, respectively. Also, four ALU designs utilizing four efficient FA circuits are presented. The proposed ALUs provide more than 74.4–23.3% improvement in the power-delay product (PDP) term compared with existing circuits. The simulation experiments reveal that with the proposed ALUs, the circuits achieve superior performance compared with previous and existing ALU designs, and the power efficiency of these units improves in a range of 18.7–20.1% over the CMOS-based units. Also, the various technology nodes and their impact are considered in this paper.

• Publisher: Springer Nature B.V
• Subject: Arithmetic and logic units / Circuit design / Circuits / CMOS / Delay time / Power consumption / Power efficiency / Scientific papers